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11 часов Π½Π°Π·Π°Π΄

Regional Principal Product Application Engineer (PCIe/CXL)

185Β 000 - 240Β 000$
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

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ОписаниС вакансии

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TL;DR
Regional Principal Product Application Engineer (PCIe/CXL): Supporting customer design-in, silicon and system bring-up, and technical issue resolution for high-speed semiconductor connectivity products with an accent on PCIe physical-layer debugging, CXL, and customer system integration. Focus on analyzing complex silicon, firmware, hardware, and system issues, coordinating internal engineering teams, and enabling real-time collaboration with Asia Pacific stakeholders during 12:00 PM to 9:00 PM PST hours.

Location: San Jose, California, United States. The role supports customers in the China region and requires working approximately from 12:00 PM to 9:00 PM PST for real-time collaboration with Asia Pacific stakeholders.

Base salary: $185,000–$240,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also be available.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and software integrating PCIe, CXL, Ethernet, NVLink, and UALink technologies.

What you will do

  • Provide technical guidance to customers and overcome design challenges involving semiconductor connectivity products.
  • Support customer development, debugging, and design-in activities across the China region.
  • Lead silicon and system bring-up, debug customer systems, and drive resolution of complex technical issues.
  • Coordinate internal development teams, FAEs, sales teams, and customer stakeholders toward issue resolution.
  • Generate technical collateral for existing and new products.
  • Provide feedback to internal teams to improve products and processes.

Requirements

  • Bachelor’s degree in Electrical Engineering required; a Master’s degree is preferred.
  • At least 3 years of experience designing in complex SoC or silicon products with high-speed interfaces, preferably PCIe.
  • Strong knowledge of PCIe LTSSM at the physical-layer level, related standards, and debugging; PCIe 5.0 experience required, with PCIe 6.0 or CXL experience preferred.
  • Experience with silicon or system bring-up and debugging in customer systems.
  • Hands-on experience with protocol analyzers, exercisers, high-speed oscilloscopes, or BERTs.
  • Full professional proficiency in written and spoken Mandarin is required for direct communication with China-region customers.

Nice to have

  • Firmware development in C and scripting with Python or equivalent programming languages.
  • Experience triaging issues across silicon, firmware, hardware board design, and system environments.
  • Experience with data center BMC implementation, BIOS configuration, PCIe or Ethernet switches or retimers, and PCIe compliance testing.
  • Understanding of data center systems, including servers, JBODs/JBOGs, networking switches, routers, and interconnects.

Culture & Benefits

  • Opportunity to support AI infrastructure and advanced semiconductor connectivity products.
  • Collaboration with hyperscalers, ecosystem partners, customers, and regional development teams.
  • Discretionary bonus, incentives, and benefits may be available.
  • Commitment to diverse ideas, backgrounds, and experiences.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’