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11 часов назад

Silicon Test Engineer (ATE & SLT)

Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Мэтч & Сопровод

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Описание вакансии

Текст:
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TL;DR
Silicon Test Engineer (ATE & SLT): Developing and optimizing automated test equipment and system-level test programs for silicon validation and production with an accent on semiconductor test methodologies, failure analysis, and yield improvement. Focus on driving new product introduction from silicon bring-up to mass production, automating test data analysis, and debugging complex hardware and firmware failures.

Location: Taipei, Taiwan

Company

hirify.global develops Trusted Control/Compute Units that combine hardware security, AI-driven resilience, efficiency, and real-time platform management for data centers and cloud and AI infrastructure.

What you will do

  • Develop, debug, and optimize ATE and SLT test programs for silicon validation and production.
  • Drive new product introduction from early silicon bring-up through mass production across multiple concurrent programs.
  • Define test requirements and methodologies with design, product, validation, foundry, and reliability teams.
  • Analyze test data to improve yield, performance, reliability, test coverage, and test efficiency.
  • Develop test patterns and support JTAG, scan, boundary scan, MBIST, and digital and analog test interfaces.
  • Automate data collection, analysis, and reporting while providing failure analysis and debug support for engineering and production samples.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or a related discipline.
  • 5+ years of industry experience in semiconductor test engineering.
  • Hands-on experience with ATE platforms such as Advantest and with system-level testing, functional testing, and system-level debug.
  • Programming and scripting experience for test development using Python, C, C++, or equivalent.
  • Strong understanding of semiconductor test methodologies, test coverage, data analysis, failure analysis, yield improvement, and test optimization.
  • Familiarity with JTAG, boundary scan, I2C, SPI, eMMC, USB, Ethernet, PCIe, data visualization tools, Confluence, and JIRA.

Culture & Benefits

  • Collaborative, cross-functional work across design, test, foundry, reliability, hardware, and firmware teams.
  • Environment focused on curiosity, execution, respect, continuous learning, and solving real-world infrastructure problems.
  • Opportunity to contribute to security and reliability technologies for critical digital infrastructure.
  • Diverse and multifaceted workplace with an emphasis on mutual support and meaningful technical impact.

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