Design Verification Engineer (AI SoC)

Location: Sunnyvale, California, United States; onsite at hirify.global's Sunnyvale office

Company

hirify.global develops AI technologies and AI silicon and systems.

What you will do

• Verify AI SoC functionality at block and SoC levels using UVM-based testbenches and directed and constrained-random tests.
• Run RTL and gate-level functional verification, debug failures, track bugs, and close coverage.
• Review specifications and architecture with design and systems engineering teams and define verification plans and coverage models.
• Develop mixed-signal co-simulation testbenches, test cases, reference models, coverage models, and regression automation.
• Support emulation and silicon bring-up debugging by reproducing hardware issues in simulation.

Requirements

• At least 5 years of UVM-based verification experience on a significantly complex project.
• Advanced knowledge of ASIC design and verification flows, simulation, testbench development, SystemVerilog, and UVM.
• Strong skills in constrained-random testing, coverage closure, gate-level simulation, X-propagation, and problem solving.
• Experience with SoC or IP verification in areas such as PCIe, Ethernet, HBM, GDDR, DDR, MMU, or cache.
• Experience with at least one scripting language, such as Perl, Python, or Tcl, and familiarity with C/C++.
• Knowledge of formal verification, including model checking and equivalence checking; excellent communication skills in English and Chinese.

Culture & Benefits

• Mission-driven work focused on advancing AI silicon and systems.
• Self-directed environment for motivated engineers.
• Opportunities to learn new skills and grow professionally.
• Small, fast-moving teams that collaborate toward ambitious goals.