15 часов назад
ASIC/SoC Functional Verification Engineer
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
ASIC/SoC Functional Verification Engineer (UVM/SystemVerilog): Verifying chiplet blocks and subsystems for photonic AI-computing infrastructure with an accent on UVM testbenches, constrained-random testing, coverage closure, and simulation-to-emulation debug. Focus on integrating UCIe VIP, validating engines against algorithmic golden models, executing mixed-signal and low-power verification, and supporting hardware-assisted signoff.
Location: San Jose, United States
Company
is a well-funded startup developing photonics infrastructure for AI supercomputing, including optical interconnects and scalable photonic engines.
What you will do
- Build and extend UVM testbenches with agents, sequences, and scoreboards for chiplet blocks and subsystems.
- Write directed and constrained-random tests, develop functional coverage, and drive functional and code coverage to closure.
- Verify in-house engines against algorithmic golden models with programmable error injection and error-pattern coverage.
- Integrate VIP such as UCIe and execute compliance, link-training, loopback, and lane-repair scenarios.
- Run regressions, triage failures, maintain CI and regression flows, and debug across simulation and emulation.
- Support register verification, firmware co-simulation, MCU boot flows, mixed-signal co-simulation, FPGA or emulation testing, gate-level simulation, and UPF signoff.
Requirements
- BS or MS in Electrical or Computer Engineering, or equivalent experience.
- 3+ years of ASIC/SoC functional verification experience.
- Strong UVM and SystemVerilog skills with constrained-random and coverage-driven verification experience.
- Experience developing block or subsystem testbenches and achieving coverage closure.
- Strong simulation debug skills and scripting experience in Python, Perl, or Tcl.
- Familiarity with regression and CI flows and failure triage.
Nice to have
- Verification experience with high-speed SerDes, PAM4, FEC, or Reed-Solomon coding.
- UCIe, PCIe/CXL, Ethernet, or UALink VIP and compliance experience.
- Mixed-signal verification using Verilog-AMS or SystemVerilog real-number models.
- Emulation, FPGA prototyping, low-power/UPF, gate-level, formal, or performance verification experience.
- Experience with NICs, Ethernet or InfiniBand switches, cache-coherent fabrics, or portable stimulus.
Culture & Benefits
- Comprehensive health, dental, and vision benefits.
- Professional development opportunities and certification support.
- Access to cutting-edge technology and cloud platforms.
- Collaborative environment with cross-functional engineering teams.
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