Staff RTL Design Engineer - CPU Midcore (RISC-V)

Location: Cambridge, England, United Kingdom. Right to work in the United Kingdom is required. Access to export-controlled technology is subject to applicable authorization or export licensing.

Company

hirify.global develops high-performance RISC-V compute platforms and CPU intellectual property for applications including AI, machine learning, automotive, data centers, mobile, and consumer devices.

What you will do

• Architect, design, and implement CPU core features, performance improvements, and RISC-V ISA extensions using Chisel.
• Integrate design content into the Chisel/FIRRTL framework and improve automated generation of documentation, verification testbenches, tests, and packaged software.
• Perform initial sandbox verification and collaborate with design verification engineers on verification plans and execution.
• Work with physical implementation engineers to meet frequency, area, and power targets.
• Collaborate with performance modeling engineers on performance exploration and optimization.
• Develop microarchitecture specifications and document design knowledge in a collaborative engineering environment.

Requirements

• BS/MS degree in computer science, computer engineering, electrical engineering, or a related field, or equivalent experience.
• 5+ years of design experience, including academic or professional CPU RTL design.
• Proficiency in hardware RTL design with Verilog, SystemVerilog, or VHDL.
• Strong software engineering background in object-oriented, aspect-oriented, and functional programming; templated metaprogramming; compiler infrastructures; and data modeling.
• Experience with test-driven development and writing adaptive unit tests.
• Attention to detail, focus on high-quality design, and effective teamwork.

Nice to have

• Experience with Scala/Chisel, Bluespec, or another software-based language or DSL for configurable hardware.
• Knowledge of RISC-V architecture and CPU processor design areas such as instruction decode, register renaming, reorder buffers, instruction scheduling, vector units, or load-store units.
• Knowledge of verification principles, testbenches, UVM, and coverage.
• Experience with Git/GitHub, Jira, or Confluence.

Culture & Benefits

• Collaborative engineering culture focused on sharing knowledge and solving complex hardware problems.
• Fast-paced environment focused on bringing high-quality, high-performance hardware IP to market.
• Equal opportunity and inclusive workplace committed to diversity.
• Employment is contingent on successful background and reference checks.