Principal Engineer - Design (SoC/FPGA)

Location: Burnaby, Canada

Annual base salary: $86,000–$186,000 USD, plus restricted stock units and quarterly bonus payments

Company

hirify.global develops technology and products that power systems around the world and operates as a large global organization.

What you will do

• Port SoC RTL to Cadence Palladium, Protium, and FPGA platforms.
• Develop emulation-specific hardware for subsystem and system-level co-verification.
• Build a common testing ecosystem for pre-silicon and post-silicon validation.
• Develop firmware and tests for pre-silicon subsystem and system-level co-verification.
• Troubleshoot complex embedded multi-core real-time systems executing emulation test plans.
• Use protocol analyzers, error injection, and defect-tracking tools to analyze issues and report verification progress.

Requirements

• BS/MS degree or higher in Electrical, Electronic, or Computer Engineering.
• 10+ years of relevant experience.
• 5+ years of experience with serial protocols such as SAS, SATA, or NVMe, plus thorough PCIe knowledge.
• Proficient Linux experience and strong programming or scripting skills in C, Python, Tcl, and Bash.
• Digital design and RTL coding experience with VHDL, Verilog, or SystemVerilog.
• Knowledge of MIPS, ARM, or RISC-V architectures, including JTAG, I2C, and firmware programming.

Nice to have

• Experience with RAID HBAs, SAS controllers, software testing strategies, test automation, and testing tools.
• Embedded Linux and RTOS development knowledge, including processes, threads, scheduling, synchronization, and memory management.
• Experience supporting Cadence infrastructure and process flows.
• Strong analytical, documentation, communication, and problem-solving skills.

Culture & Benefits

• Full-time position in a fast-paced engineering environment.
• Health benefits begin on the first day.
• Retirement savings plans and an employee stock purchase program with a six-month look-back feature.
• Total compensation includes base pay, restricted stock units, and quarterly bonuses.
• Travel expectation is 0%–25%.