Digital Design Engineer Lead (DDR5)

Location: Chengdu, China

Company

hirify.global develops integrated power semiconductors and system power delivery architectures.

What you will do

• Define architecture and micro-architecture for DDR5 SPD Hub features.
• Develop and lead RTL for I3C, I²C, RCD/SPD Hub control logic, ECC/parity, and protection mechanisms.
• Lead digital design verification and test case development using Verilog, SystemVerilog, and UVM.
• Collaborate with digital, analog/mixed-signal, DFT, physical design, firmware, and validation teams during chip integration.
• Support engineering sample bring-up, validation, and failure analysis.
• Prepare design specifications, timing diagrams, test plans, and integration guides.

Requirements

• MS or PhD degree with 10+ years of digital ASIC design experience.
• Experience with memory subsystem architecture, preferably DDR4/DDR5 or SPD/RCD devices.
• Experience developing DDR5 SPD Hub or RCD/PMIC products.
• Knowledge of I3C/MIPI, I²C/SMBus, or SPD EEPROM behavior.
• Experience with security logic, including encryption and authentication fundamentals.
• Strong knowledge of ASIC development processes, digital design techniques, and scripting or programming with Perl, TCL, Unix, Python, or C/C++.

Nice to have

• Embedded design or firmware development experience.
• Knowledge of power management applications or mixed-signal design.
• Experience with I2C, I3C, SPI, USB, PMBUS, or USB-PD.

Culture & Benefits

• Work in a semiconductor company focused on creativity, sustainability, and leading-edge product innovation.
• Collaborate with multidisciplinary engineering teams on system power delivery technologies.
• Equal opportunity employment and a commitment to diversity.