Principal Engineer - Digital Design (Ethernet PHY)

Location: Cork, Ireland; onsite role. Travel: 0%–25%.

Company

hirify.global develops semiconductor products, networking ICs, and software for automotive and industrial applications.

What you will do

• Architect and develop digital blocks for digital ASIC products and serial communication PHY layers.
• Write RTL code using Verilog, SystemVerilog, or VHDL.
• Perform functional verification and bit-matching against system models.
• Develop pre-silicon FPGA emulation and support synthesis, static timing analysis, and ASIC design-flow activities.
• Collaborate with system architects, analog/mixed-signal designers, verification, validation, firmware, and PTE teams during silicon bring-up.
• Lead design reviews, documentation, and technical mentoring for junior engineers.

Requirements

• Bachelor’s degree in science, engineering, or a related field.
• 10+ years of experience in digital ASIC design.
• Experience with RTL coding in Verilog, SystemVerilog, or VHDL.
• Strong knowledge of high-speed, asynchronous, and low-power circuit design.
• Strong knowledge of the digital IC development flow.
• Experience working with global teams.
• Familiarity with functional verification using Verilog or SystemVerilog.

Nice to have

• Experience with automotive and industrial Ethernet standards, including 802.3bp, 802.3ch, or 802.3cg.
• Experience with mixed-signal designs.
• Knowledge of DSP algorithms and communication systems.

Culture & Benefits

• Work within a global organization with teams across multiple locations.
• Collaborative, cross-functional, and cross-site engineering environment.
• Culture focused on trust, empowerment, respect, diversity, communication, employee development, and stability.
• Leadership and career-development programs are available.