Lead DFT Engineer (Edge Computing)

Location: Bangalore, India

Company

hirify.global develops advanced AI hardware and software systems for edge-to-cloud computing, based on in-memory computing technology for high-efficiency and high-density processing.

What you will do

• Define and implement end-to-end DFT architectures for complex SoCs, including hierarchical DFT, scan compression, boundary scan, and MBIST.
• Develop in-system test and power-on self-test strategies for reliable operation in remote edge data centers.
• Oversee scan insertion, ATPG for stuck-at, transition, and path-delay faults, and memory and logic BIST implementation.
• Collaborate with Design, Physical Design, and Yield teams to maximize test coverage while minimizing area, power, and timing impact.
• Lead post-silicon bring-up and debugging on ATE, root-causing silicon failures and optimizing test time.

Requirements

• 12+ years of DFT experience, including at least 2 years in a leadership or principal role.
• Expertise with Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Modus.
• Deep experience with MBIST and repair, SCAN, IJTAG (IEEE 1687), and boundary scan (IEEE 1149.1/6).
• Proven experience with 7nm, 5nm, or smaller FinFET nodes.
• Experience managing DFT for multi-voltage and power-gated designs.

Culture & Benefits

• Work on next-generation AI hardware and software for power- and space-constrained edge applications.
• Contribute to silicon development led by experienced semiconductor and AI systems technologists.
• Focus on high compute efficiency, manufacturability, reliability, and edge deployment.