Principal Electrical Engineer (Smart Cable Modules)

Location: Shanghai, China

Company

hirify.global develops rack-scale AI infrastructure and connectivity solutions based on CXL, Ethernet, NVLink, PCIe, and UALink technologies, complemented by its COSMOS software suite.

What you will do

• Own the end-to-end electrical architecture and roadmap for Smart Cable Modules targeting 400G, 800G, and beyond.
• Define SerDes channel topology, power delivery, thermal budgets, PCB standards, layout rules, and SI/PI guidelines.
• Lead schematic capture, PCB design reviews, component selection, technical reviews, and high-speed design sign-off.
• Drive module management hardware, including I2C topology, register maps, microcontroller selection, diagnostics, clocking, ESD protection, and supervisory circuitry.
• Lead hardware bring-up, validation, firmware integration testing, failure analysis, and DFT/DFM improvements with contract manufacturers.
• Collaborate with firmware, software, suppliers, hyperscale customers, and standards organizations while mentoring hardware engineers.

Requirements

• Bachelor’s or Master’s degree in electrical engineering or a closely related field.
• 10–12+ years of progressive electrical engineering experience, including at least 5 years with high-speed SerDes interconnects, active copper cables, or optical/pluggable modules.
• Production hardware architecture and delivery experience with 56G, 112G, or faster SerDes interfaces such as Ethernet, PCIe, or InfiniBand.
• Expert signal integrity knowledge covering impedance control, differential pairs, eye-mask budgeting, channel loss allocation, and PCB layout review.
• Experience with Cadence Allegro or OrCAD, OSFP, QSFP-DD800, SFP-DD, CMIS 5.x, SFF-8636, I2C/MDIO, PDN design, and mixed-signal hardware debug.
• Demonstrated ability to lead board bring-up, use high-bandwidth oscilloscopes and protocol analyzers, and work with silicon vendors on reference designs, errata, and platform bring-up.

Nice to have

• Architecture or lead-engineer experience on 800G or higher module programs.
• Familiarity with co-packaged optics, linear-drive modules, host switching ASIC interfaces, or SerDes equalization.
• Participation in OIF, IEEE 802.3, or QSFP/OSFP MSA standards bodies.
• Experience with PCIe Gen 5/6 retimer modules.
• Python scripting for lab automation, measurement-data reduction, or hardware characterization.

Culture & Benefits

• Work with cross-functional engineering teams, contract manufacturers, silicon vendors, hyperscale customers, and industry standards organizations.
• Contribute to technical mentoring, strategic hiring, onboarding, and engineering process improvement.
• The organization encourages applications from people with diverse backgrounds and experiences.