Senior ALU Design Engineer (RISC-V)

Location: Cambridge, England, United Kingdom; hybrid work with one office day per week expected

Company

hirify.global develops high-performance RISC-V compute platforms for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer electronics.

What you will do

• Specify, design, and implement arithmetic operators for RISC-V instructions, including floating-point, vector, cryptographic, and integer operations.
• Optimize existing operators for timing, area, power consumption, and latency.
• Develop unit and formal tests for optimized and newly designed hardware.
• Collaborate with the physical implementation team to meet frequency, area, and power targets.
• Create high-quality technical documentation and collaborate across engineering disciplines.

Requirements

• Master’s degree or higher in electronic engineering, computer science with a strong mathematical background, or a related field with strong code development experience.
• At least 2 years of RTL design or related design experience.
• Academic or professional experience with arithmetic RTL or CPU RTL design using Chisel, Verilog, SystemVerilog, or VHDL.
• Knowledge of at least one object-oriented or functional programming language and willingness to adopt Chisel hardware-generator design.
• Strong attention to detail and commitment to high-quality code and documentation.
• Right to work in the United Kingdom is required. Successful background and reference checks are also required, along with authorization to access export-controlled technology or the ability to obtain the necessary approvals.

Culture & Benefits

• Hybrid working with one expected office day per week; additional office days are possible by preference.
• Collaborative engineering environment focused on teamwork and cross-disciplinary cooperation.
• Inclusive workplace committed to diversity and equal opportunity.