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Design Technology Tool Enablement Engineer (EDA)

173 660 - 284 580$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

Текст:
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TL;DR
Design Technology Tool Enablement Engineer (EDA): Designing, developing, testing, and debugging EDA software tools and automated flows for semiconductor process design and manufacturing with an accent on rule-deck development, physical verification, and process technology enablement. Focus on translating physical design challenges into algorithmic solutions, automating workflows, and validating tool performance across design methodologies.

Location: Hybrid role based at hirify.global sites in Hillsboro, Oregon; Phoenix, Arizona; or Santa Clara, California, United States

Annual salary: $173,660–$284,580 USD

Company

hirify.global Foundry develops semiconductor process and packaging technologies, manufacturing capabilities, and supply-chain solutions for customers worldwide.

What you will do

  • Design, develop, test, and debug EDA software tools and methodologies for semiconductor process design and manufacturing.
  • Define technology specifications with process developers, design rule owners, end users, and external EDA vendors.
  • Automate workflows to improve efficiency, accuracy, and deployment across design teams.
  • Build and execute test cases to validate tool functionality and integration with design methodologies.
  • Assess performance contributors and isolate issues affecting technology enablement.
  • Analyze complex problems and translate physical design challenges into software-driven solutions.

Requirements

  • Master’s degree in Electrical Engineering, Computer Engineering, or a related STEM field with 8+ years of experience, or a Ph.D. in a related field with 5+ years of experience.
  • 3+ years of scripting experience with Python, Tcl, or Perl for automation or testing on Unix/Linux platforms.
  • 3+ years of experience with EDA tools such as Calibre, ICV, or Pegasus, including rule-deck development using SVRF/TVF, PXL, or PVL.
  • 5+ years of experience in semiconductor device physics or process technology, design rules, or algorithmic solutions for physical design challenges.
  • Strong analytical, problem-solving, communication, organization, and cross-functional collaboration skills.

Nice to have

  • Familiarity with DRC, LVS, and density/fill physical verification modules.
  • Experience with Cadence Virtuoso or Synopsys Custom Designer.
  • Leadership in process improvement or innovation initiatives.

Culture & Benefits

  • Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
  • Competitive pay with stock bonuses.
  • Health, retirement, and vacation benefits.
  • Work in a dynamic, cross-functional, and sometimes ambiguous environment.

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