Principal Physical Design Engineer (RTL-to-GDSII)

Location: Bangalore, hybrid

Company

hirify.global develops advanced AI hardware and software systems for edge-to-cloud computing, based on in-memory computing technology for power-, energy-, and space-constrained applications.

What you will do

• Lead full-flow implementation of large, high-speed blocks and SoCs from synthesis through sign-off using the Cadence Digital Suite.
• Optimize power, performance, and area by analyzing library cells, metal stacks, PDK constraints, and EDA tool engines.
• Build and refine robust, repeatable push-button execution methodologies that minimize manual iterations.
• Collaborate with RTL, architecture, and DFT teams to bring physical constraints into early design decisions.
• Identify runtime, convergence, and tool limitations and develop automated solutions to remove execution bottlenecks.
• Mentor the physical design team and work with front-end, foundry, and EDA vendor partners.

Requirements

• 14+ years of physical design experience with multiple sub-5nm tape-outs.
• Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus.
• Deep knowledge of sub-5nm physics, including EUV constraints, multi-patterning, FinFET, and IR/EM challenges.
• Expertise in static timing analysis, physical verification, power integrity, and ECO methodology.
• Proficiency in Tcl and Python for custom flow wrappers and PPA data-mining tools.
• Ability to apply first-principles thinking, influence architecture and RTL decisions, and build strong technical relationships across teams.

Culture & Benefits

• Autonomy to overhaul legacy physical design flows.
• Opportunity to work on cutting-edge 3nm and 2nm semiconductor nodes.
• Focus on first-principles engineering rather than blindly following vendor best practices.
• Resources to develop scalable and predictable silicon implementation methodologies.