Design Verification Engineer (SerDes)

Location: Remote from Romania, with preference for residence in Iași; primary location listed as Bucharest, Romania. Shift 1, Romania.

Company

hirify.global is an independent FPGA company developing programmable logic devices for data centers, telecommunications infrastructure, AI accelerators, and industrial systems.

What you will do

• Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models, and assertions.
• Run simulations, analyze failures, and debug RTL and testbench issues.
• Collaborate with design, architecture, and analog teams on block-level and top-level verification.
• Verify high-speed SerDes IP used in PCIe, Ethernet, and other standard interfaces.

Requirements

• BSc in Electrical Engineering, Computer Engineering, or an equivalent field.
• 0–5 years of experience in digital design or verification, including internships, academic projects, or industry experience.
• Working knowledge of SystemVerilog and basic familiarity with UVM concepts.
• Understanding of synchronous logic, FSMs, pipelining, and clock domain crossing.
• Strong analytical and debugging skills.
• Good spoken and written English is required.

Culture & Benefits

• Work alongside experienced engineers on silicon shipped to production.
• Opportunity to build deep technical expertise in high-speed silicon verification.
• Responsibility and ownership increase as technical proficiency develops.
• Regular full-time employment.