19 часов назад
Principal Analog Mixed-Signal Design Engineer (AI Connectivity)
165 000 - 210 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal Analog Mixed-Signal Design Engineer (AI Connectivity): Architecting and designing high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O in rack-scale AI infrastructure with an accent on PLLs, LDOs, data converters, clocking, and advanced FinFET nodes. Focus on taking designs from architecture through silicon bring-up, validating performance across PVT corners, debugging silicon, and mentoring analog engineers.
Location: Toronto, Ontario, Canada
Salary: $165,000–$210,000 annually, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.
Company
provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.
What you will do
- Architect and design high-speed analog and mixed-signal circuits, including PLLs, LDOs, references, SerDes building blocks, ADCs, DACs, and clocking circuits.
- Drive circuit development from specifications and architecture through schematic design, layout supervision, and verification across PVT corners.
- Develop robust designs in advanced FinFET process nodes while balancing power, area, and performance.
- Lead silicon bring-up, characterization, debugging, and root-cause analysis with validation and product engineering teams.
- Define test plans and correlate silicon performance with design targets.
- Set design methodologies and review standards, collaborate across engineering functions, and mentor analog engineers.
Requirements
- MS or PhD in Electrical Engineering or a related field.
- 8+ years of experience in analog and mixed-signal integrated circuit design.
- Proven experience designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS or FinFET nodes.
- Strong knowledge of physical-layer design, signal integrity, and high-speed I/O.
- Proficiency with industry-standard design and simulation tools, including Cadence Virtuoso and Spectre.
- Strong layout and parasitic-aware design skills.
Nice to have
- Experience taking multiple analog or mixed-signal designs through production tape-out and high-volume manufacturing.
- Expertise in PCIe, Ethernet, UALink, UCIe, and related PHY architectures.
- Experience with silicon debugging, ATE test development, and design-for-test techniques.
- Experience mentoring engineers and leading technical design reviews.
- Excellent communication skills and a collaborative, ownership-driven mindset.
Culture & Benefits
- Opportunity to work on connectivity technologies for advanced AI data-center infrastructure.
- Cross-functional collaboration with digital, physical design, systems, architecture, validation, and product engineering teams.
- Discretionary bonus, incentives, and benefits may be available.
- Commitment to an inclusive workplace that welcomes diverse backgrounds and experiences.
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