Manager, Package Design Engineering

Location: San Jose, California, United States

Salary: $230,000–$265,000 USD base salary

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and a software suite integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies.

What you will do

• Build, mentor, and scale a package design engineering team with clear ownership and execution processes.
• Lead end-to-end FCBGA, FCCSP, monolithic, multi-die, and chiplet-based package design from feasibility through tape-out and production ramp.
• Define substrate stack-ups, pad stacks, routing strategies, and design constraints for electrical, thermal, mechanical, and manufacturing requirements.
• Drive chip-package-board co-design with SIPI, silicon architecture, system, board, and product teams.
• Collaborate with OSATs and substrate vendors on feasibility, manufacturability, design rules, and technology roadmaps.
• Develop design standards, automation flows, and scalable methodologies across multiple product programs.

Requirements

• Bachelor’s degree in Electrical Engineering, Materials Science, or a related field.
• 10+ years of progressive IC package design experience using tools such as Cadence Allegro APD/SiP.
• 5+ years of leadership experience managing teams or technical organizations in IC packaging.
• Hands-on experience delivering HVM-ready FCBGA/FCCSP packages using Cadence APD.
• Experience with high-speed SerDes systems, including PCIe Gen5/6/7, CXL, and 100G/200G/400G+ Ethernet, as well as 7nm, 5nm, and 3nm nodes.
• Deep knowledge of substrate technologies, stack-ups, routing constraints, assembly processes, SI/PI fundamentals, OSAT collaboration, and production ramp.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience with 2.5D/3D packaging, chiplets, heterogeneous integration, CPO/CPC, or advanced packaging platforms.
• Automation and scripting experience with Python, SKILL, or Tcl.
• Background in package feasibility, platform evaluation, technology roadmaps, chip floor planning, SIPI analysis, thermal performance, or mechanical performance.

Culture & Benefits

• Work in an innovation-focused environment developing connectivity products for AI infrastructure and hyperscale customers.
• Collaborate across silicon architecture, SIPI, PCB, validation, manufacturing, OSAT, and substrate-vendor organizations.
• Shape package design methodology, scalable standards, and chip-package-board co-design frameworks across multiple product lines.
• Base salary is determined by location, experience, and compensation for similar positions.
• The position may be hired at Manager or Director level.