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11 часов назад

Staff Analogue Designer (CMOS Modelling)

Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
UK/US/SK +4 еще
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Staff Analogue Designer (CMOS Modelling) (Cryo-CMOS and mixed-signal modelling): Building behavioural full-chip models for cryo-CMOS integrated circuits that control trapped-ion quantum processors with an accent on Verilog-A, Verilog-AMS, real-number modelling, and model correlation. Focus on deriving robust models from mathematical analysis, establishing mixed-signal co-simulation and regression flows, and defining modelling standards and sign-off criteria for tapeout decisions.

Location: Oxford, England, United Kingdom, based in the Oxford office with the option to work remotely a few days per week. Travel up to 5%.

Company

hirify.global develops integrated quantum computing, networking, sensing, and security solutions, including trapped-ion quantum processors and cryo-CMOS control systems.

What you will do

  • Own the full-chip CMOS modelling strategy, including architecture, abstraction levels, accuracy targets, and sign-off criteria.
  • Develop Verilog-A and Verilog-AMS models for analogue blocks such as references, DACs, switches, regulators, and clock distribution.
  • Build real-number models with SystemVerilog nettypes/UDNs and legacy wreal for digital verification and regression.
  • Derive behavioural models from mathematical descriptions, including transfer functions and Z-parameter networks.
  • Run model-versus-schematic correlation and incorporate measured silicon behaviour into the modelling flow.
  • Establish mixed-signal co-simulation and regression using Cadence AMS Designer, Xcelium, and Spectre; contribute to design reviews and mentor engineers.

Requirements

  • 10+ years of deep analogue and mixed-signal design and modelling experience, ideally with production tapeout flows.
  • Expertise in Verilog-A, Verilog-AMS, and real-number modelling.
  • Strong mathematical foundations in linear systems, Laplace and z-domain analysis, network parameters, noise, and non-linearity.
  • Fluency with production Cadence flows and tools such as Virtuoso, Spectre, Xcelium, and AMS Designer or similar.
  • Experience with SystemVerilog, MATLAB, or Python/NumPy for analysis and model validation.
  • Ability to collaborate with analogue designers, verification engineers, and system engineers in a highly technical environment.

Nice to have

  • Experience with extreme-environment silicon, including cryogenics or space.
  • Experience defining modelling standards, fidelity levels, and sign-off criteria across an IC development flow.

Culture & Benefits

  • Autonomy, productivity, respect, and an inclusive working environment.
  • Comprehensive medical, dental, and vision plans.
  • Matching 401(k), unlimited PTO, and paid holidays.
  • Parental and adoption leave, legal insurance, and a home technology stipend.
  • Employment is subject to export-control and government-contract compliance requirements, including additional immigration-status verification.

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