Назад
Company hidden
обновлено 6 дней назад

Principal Engineer - Design (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Principal Engineer - Design (Semiconductor): Leading digital design, DFT, physical implementation, synthesis, and STA signoff for advanced-node integrated circuits in optical networking and connectivity devices with an accent on RTL-to-netlist generation, MMMC timing analysis, and high-speed macro and subsystem flows. Focus on developing design constraints, debugging synthesis and timing issues, coordinating with RTL, DFT, and APR teams, and supporting tapeout for 16 nm or smaller technologies.

Location: Saskatoon, Canada

Company

hirify.global develops semiconductor products for optical networking, connectivity, telecom, and hyperscale data center applications.

What you will do

  • Lead digital design, DFT, physical implementation, synthesis, and static timing analysis for block-level and full-chip integrated circuit designs.
  • Develop macro constraints, memory generations, synthesis configurations, and flows for high-speed macros and subsystems.
  • Own STA signoff across multiple design hierarchy levels, operating modes, and process corners.
  • Ensure the quality of pre- and post-netlist deliverables through CLP, LEC, and in-house tool checks.
  • Collaborate with RTL, DFT, APR, and project teams on constraints, floorplanning, macro placement, and implementation quality.
  • Support advanced-node product development through tapeout and production release.

Requirements

  • Bachelor’s or graduate degree in computer science, electrical/electronics engineering, or VLSI engineering.
  • At least 10 years of experience in synthesis, STA, and formal verification using mainstream tools.
  • Hands-on experience with RTL design, synthesis, UPF/CPF low-power logic insertion, and macro- and SoC-level STA signoff.
  • Experience with Cadence Genus or Synopsys DC/FC, timing models, DFT, libraries, and hierarchical budgeting flows.
  • Strong coding and scripting skills in TCL, Perl, or Python, with excellent analytical and debugging abilities.
  • Tapeout experience on at least one project using 16 nm or smaller silicon process technologies; strong English communication skills required.

Culture & Benefits

  • Full-time position within a large global semiconductor organization.
  • Work with advanced process nodes, optical networking devices, and cloud connectivity technologies.
  • Access to employee development and leadership growth programs.
  • Travel expectation: 0%–25%.
  • Culture emphasizes trust, empowerment, respect, diversity, communication, and values-based decision-making.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →