Principal Engineer - Design (Semiconductors)

Location: Saskatoon, Canada

Company

hirify.global develops semiconductor products, including high-speed optical networking and connectivity solutions for telecom and hyperscale data center networks.

What you will do

• Lead digital design, DFT, physical implementation, and static timing analysis at block and full-chip levels.
• Develop synthesis, STA, and layout constraints, RAM generations, and flows for high-speed macros and subsystems.
• Own STA signoff across multiple design hierarchy levels, modes, and corners.
• Develop and improve RTL synthesis methodologies using Cadence and Synopsys tools.
• Validate pre- and post-netlist deliverables through CLP, LEC, and internal tool checks.
• Collaborate with RTL, DFT, and APR teams on constraints, floorplanning, macro placement, and deliverable quality.

Requirements

• Bachelor’s or graduate degree in computer science, electrical/electronics engineering, or VLSI engineering.
• At least 10 years of experience in synthesis, STA, and formal verification using mainstream tools.
• Hands-on experience with RTL design, synthesis, UPF/CPF low-power logic insertion, and macro- and SoC-level STA signoff.
• Experience with Cadence Genus or Synopsys DC/FC, plus strong scripting skills in Tcl, Perl, or Python.
• Understanding of timing models, DFT, libraries, and hierarchical budgeting flows.
• Tapeout experience on at least one project using a 16 nm or smaller silicon process; strong English communication skills required.

Culture & Benefits

• Full-time role within a large global semiconductor organization.
• Participation in the full semiconductor R&D lifecycle, from concept and design through validation and production release.
• Access to employee development and leadership growth programs.
• Travel requirement of 0%–25%.