Senior ASIC Design Engineer (AI)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
TL;DR
Senior ASIC Design Engineer (AI): Leading the micro-architecture and RTL design for high-performance automotive communication SoCs with an accent on protocol integration, timing analysis, and power-performance-area optimization. Focus on building custom silicon architectures to support real-time sensor data and Physical AI applications in software-defined vehicles and robotics.
Location: Must be based in or able to commute to Toronto, Canada (Hybrid)
Company
is a well-funded startup developing breakthrough Ethernet-based networking technology and custom silicon to power the future of autonomous vehicles, robotics, and intelligent machines.
What you will do
- Define micro-architecture specifications for complex digital SoCs from concept to final delivery.
- Develop RTL designs and oversee synthesis, linting, CDC, LEC, and static timing analysis.
- Collaborate with system architects, hardware, software, and verification teams to deliver high-performance silicon.
- Specify internal and external interactions, data flow, processing algorithms, and software interfaces.
- Ensure design meets rigorous power, performance, and area goals for automotive-grade applications.
- Operate with high autonomy as a self-starter in a collaborative international environment.
Requirements
- Must be based in or able to commute to Toronto, Canada
- BS or MS in Electrical Engineering, Computer Science, or equivalent field.
- Minimum 10+ years of professional experience in ASIC RTL design and architecture.
- Deep understanding of digital design fundamentals, methodologies, and simulation tools.
- Extensive experience with Verilog and SystemVerilog.
- Proven track record in the development and delivery of complex System-on-Chip (SoC) architectures.
Nice to have
- Experience with networking protocols such as Ethernet (MAC, PHY/PCS), Switching, TCP/IP, or PCIe.
- Proficiency in digital signal processing (DSP) filters or digital mixed-signal modeling.
- Background in IP integration (SerDes, controllers, processors) or video standards.
- Scripting and programming skills in Perl, TCL, C/C++, or Make.
Culture & Benefits
- Equity in a high-growth, well-funded startup with pre-IPO stock options.
- Opportunity to work on cutting-edge automotive and AI hardware at a technology-focused organization.
- Competitive base salary and comprehensive medical, dental, and vision insurance.
- Flexible work hours to support work-life balance in a hybrid environment.
- Exposure to world-class talent and career growth aligned with company scaling.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β