Principal Engineer, Design Verification (DDR Memory Subsystems)

Location: San Jose, California, United States. Applicants must be eligible for any required U.S. export authorizations.

Salary: $209,500–$299,200 USD annually for the Bay Area California region.

Company

hirify.global is a pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, edge computing, and embedded systems.

What you will do

• Lead design verification for complex DDR memory subsystems across multiple FPGA product families.
• Define verification architecture, methodology, strategy, and plans for DDR controllers, PHYs, training logic, calibration flows, and subsystem integration.
• Architect reusable UVM/SystemVerilog environments with constrained-random verification, assertions, functional coverage, scoreboarding, protocol checking, and regression automation.
• Drive coverage closure, debug, root-cause analysis, and metric-based verification execution.
• Collaborate with Architecture, RTL Design, Physical Design, Firmware, System Validation, and Silicon Engineering teams.
• Mentor senior verification engineers and support post-silicon bring-up, characterization, and system validation.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 15+ years of design verification experience with complex ASIC, SoC, or FPGA products.
• 10+ years verifying DDR memory subsystems, including memory controllers and PHY architectures.
• Expertise in SystemVerilog, UVM, SystemVerilog Assertions, constrained-random verification, functional coverage, and verification planning.
• Knowledge of DDR4, DDR5, LPDDR4, LPDDR5, HBM, AXI, AMBA, cache coherency, memory initialization, training, calibration, and subsystem integration.
• Experience leading complex verification from specification through silicon validation, with strong debugging and cross-functional communication skills.

Nice to have

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with PCIe, Ethernet, CXL, UCIe, SerDes, formal verification, emulation, FPGA prototyping, or post-silicon validation.
• Python, Perl, Tcl, or Shell scripting for automation and infrastructure development.
• Experience with CI/CD pipelines, scalable regression frameworks, and organization-wide verification methodology leadership.

Culture & Benefits

• Opportunity to shape verification strategy across multiple FPGA product generations.
• Work on memory subsystem technologies supporting AI, cloud, networking, and edge applications.
• Cross-functional engineering collaboration and influence on architecture decisions.
• Incentive opportunities based on individual and company performance.