Hardware Design Engineering, Senior Director - Signal Connectivity Rack-Scale Platforms

Location: San Jose, California, United States

Base salary: $220,000–$280,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global develops semiconductor-based connectivity solutions, software, cables, evaluation platforms, and rack-scale products for AI infrastructure.

What you will do

• Lead and scale a multidisciplinary hardware design engineering organization covering electrical and PCB design, mechanical engineering, validation, lab infrastructure, and customer hardware engineering.
• Define technology roadmaps for active electrical cables, smart cable modules, silicon evaluation platforms, and rack-scale systems.
• Oversee product development from architecture, schematic and layout design through mechanical design, prototyping, validation, qualification, and production release.
• Drive high-speed interconnect, signal integrity, power delivery, thermal, connector, chassis, and form-factor design decisions for module- and system-level products.
• Build hardware validation programs and engineering labs supporting 112G/224G characterization, reliability testing, interoperability, and failure analysis.
• Lead OEM design enablement and customer technical support, including reference designs, design reviews, integration guidance, bring-up, debugging, and issue resolution.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 18+ years of progressive hardware design engineering experience and 8+ years in engineering management or leadership roles, including managing managers.
• Deep expertise in high-speed PCB/substrate design, signal integrity, power delivery, and mixed-signal circuits at 56G/112G PAM4 or higher.
• Strong experience with mechanical engineering for interconnect and system products, including connector design, thermal management, chassis architecture, and form-factor compliance.
• Experience establishing hardware validation programs, managing engineering labs, and taking products through qualification and volume production.
• Experience with OEM hardware design enablement, contract manufacturers, and ODMs in Asia; Mandarin proficiency is preferred for manufacturing-partner engagement.

Nice to have

• Experience with AEC, SCM, optical transceivers, silicon evaluation platforms, rack-scale systems, or AI infrastructure hardware.
• Experience with 224G/lane interconnects, retimer ASIC integration, high-density backplanes, thermal and airflow architecture, and BMC interfaces.
• Familiarity with IEEE 802.3ck/dj, OIF CEI-112G/224G, CMIS, OSFP, QSFP-DD, and OCP specifications.
• Experience with FMEA, DFMEA, robust design, Six Sigma, and simulation or EDA tools such as Cadence, Ansys, Keysight, SolidWorks, or Creo.

Culture & Benefits

• Work with hyperscalers, OEMs, silicon teams, manufacturing partners, and ecosystem companies building next-generation AI infrastructure.
• Lead an organization during a period of hyper-growth, with responsibility for hiring plans, career development, technical competency models, and lab expansion.
• Collaborate across signal integrity, firmware, NPI, manufacturing, quality, reliability, product management, sales, and customer engineering.
• Support diverse perspectives and inclusive participation across backgrounds and experiences.