Director of Hardware Design Engineering (Silicon Validation Platforms & Rack-Scale Design)

Location: Based in Taiwan, preferably the Hsinchu or Taipei area, with willingness to travel across Asia and regularly to the US headquarters.

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions and its COSMOS software suite.

What you will do

• Establish and lead the Taiwan hardware engineering center as hirify.global’ primary Asia-based hub.
• Build and manage multidisciplinary teams covering electrical and PCB design, mechanical engineering, validation, applications engineering, and lab operations.
• Serve as the primary hardware engineering interface for OEM customers integrating retimers, re-drivers, connectivity ASICs, PCIe switches, and CXL switches.
• Own the architecture and delivery of silicon validation and evaluation boards for bring-up, characterization, and customer evaluation.
• Lead hardware design for AI chassis-class systems, switch trays, CEM cards, backplanes, power systems, cooling, and management subsystems.
• Build Taiwan lab infrastructure and coordinate validation, ODM collaboration, manufacturing readiness, and alignment with the Santa Clara engineering organization.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• 15+ years of progressive hardware design engineering experience and 5+ years in engineering management or leadership.
• Experience designing complex high-speed PCBs at 56G/112G PAM4 or above, including evaluation, system, backplane, or midplane designs.
• Strong experience with silicon evaluation platforms, rack-scale or chassis-class systems, signal integrity, power delivery, thermal management, and high-speed PCB design.
• Experience building engineering teams and establishing new engineering site operations, plus working with ODM partners and contract manufacturers in Asia.
• Excellent communication skills in English and Mandarin or another relevant Asian language; based in Taiwan and willing to travel across Asia and to US headquarters.

Nice to have

• Master’s or Ph.D. in Electrical Engineering focused on high-speed digital design, signal integrity, or power electronics.
• Experience with retimer, re-driver, PCIe, CXL, or high-speed SerDes evaluation platforms and 224G/lane interconnect technology.
• Experience developing rack-scale products for hyperscale cloud or AI infrastructure customers.
• Knowledge of IEEE 802.3, OIF CEI, PCIe, CXL, SFF-TA, CMIS, and OCP standards.
• Mandarin fluency at native or near-native level, or Japanese or Korean proficiency.

Culture & Benefits

• Significant autonomy in establishing the Taiwan engineering center while maintaining strategic alignment with global engineering leadership.
• Opportunity to build local lab capabilities for silicon bring-up, rack-scale testing, customer demonstrations, and interoperability validation.
• Cross-functional collaboration with OEMs, ODMs, contract manufacturers, silicon, firmware, signal integrity, validation, manufacturing, product management, sales, and FAE teams.
• Inclusive environment that encourages applications from people with diverse backgrounds and experiences.