Principal Design Verification Engineer (RISC-V)

Location: Santa Clara, California, United States

Base pay range: $231,444–$282,876 per year, with possible variable or incentive compensation and equity.

Company

A semiconductor and compute-platform company advancing high-performance RISC-V processor technology for AI, machine learning, automotive, data center, mobile, and consumer applications.

What you will do

• Lead verification planning, execution, and signoff for a scalable cache-coherent interconnect from block level through subsystem integration.
• Define test plans, assertions, checkers, scoreboards, stimulus strategies, closure criteria, and coverage models.
• Verify coherent traffic, ordering, backpressure, flow control, buffering, arbitration, QoS, error handling, bridges, and protocol adaptation layers.
• Develop directed and constrained-random scenarios covering coherency, concurrency, credits, ordering, fairness, and performance-sensitive traffic.
• Apply simulation, formal verification, emulation, and performance-oriented verification techniques while driving root-cause analysis and durable issue closure.
• Influence verification methodology and infrastructure, collaborate across architecture, RTL, formal, and performance teams, and mentor engineers.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of CPU, subsystem, SoC, or ASIC functional verification experience at Principal/T6 depth.
• Hands-on experience with SystemVerilog-based verification and reusable infrastructure for complex hardware subsystems.
• Deep knowledge of cache-coherent systems, on-chip interconnects, CPU memory subsystems, ordering, snooping, and flow-control semantics.
• Experience creating verification plans, assertions, checkers, scoreboards, coverage models, and debug workflows.
• Strong Python or similar scripting, software, automation, technical communication, and cross-functional collaboration skills.

Nice to have

• Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance CPU or SoC environments.
• Experience with memory consistency, weak ordering, multicore coherency, formal verification, emulation, or performance-oriented verification.
• Technical leadership demonstrated through mentoring, methodology improvements, and cross-team execution.

Culture & Benefits

• Collaborative environment spanning architecture, RTL, formal, performance, and design verification teams.
• Opportunity to influence reusable infrastructure and verification practices across the broader interconnect organization.
• Comprehensive benefits package that may include healthcare, retirement plans, and paid time off.
• Employment is subject to background and reference checks and verification of the right to work in the United States.
• Access to export-controlled technology requires applicable authorization or successful acquisition of necessary export licenses or approvals.