Design Verification Engineer to Staff Engineer (Unit Level Test)

Location: Hsinchu, Taiwan

Company

hirify.global develops high-performance RISC-V compute platforms for applications including artificial intelligence, machine learning, automotive, data centers, mobile, and consumer devices.

What you will do

• Collaborate with CPU designers, compiler, performance, and system verification teams to generate automated test cases.
• Review product definitions and specifications from a verification perspective and contribute to feature specifications and test plans.
• Develop checkers and assertions for memory subsystem designs and interconnects.
• Build and maintain scalable constrained-random test benches, verification tools, test suites, and in-house verification IP.
• Write functional coverage, analyze code and functional coverage results, and close coverage gaps.
• Perform failure analysis and troubleshoot verification issues across processor and SoC designs.

Requirements

• 3+ years of recent experience with standard design verification tools and methodologies.
• Experience with SystemVerilog/UVM, Verdi or DVE, Verilog, Makefiles, and scripting languages.
• Understanding of processor and SoC architecture, or the ability and motivation to learn it.
• Thorough knowledge of verification flows, including test planning, test generation, failure analysis, coverage analysis, and coverage closure.
• Strong troubleshooting, analytical, and interpersonal skills.
• Successful background and reference checks and proof of the right to work in Taiwan are required. Access to export-controlled technology is subject to applicable authorization or export licensing.

Nice to have

• Familiarity with the AMBA protocol.

Culture & Benefits

• Flexible work environment.
• Generous time-off policy.
• Employee stock option program.
• Pension scheme.
• Reasonable accommodation is available for candidates with disabilities during the application and employment process.