Lead Design Engineer (Verification)

Location: Shanghai (Onsite)

Company

A global leader in electronic design innovation, providing software, hardware, and IP to help customers build great products.

What you will do

• Develop and execute verification plans for SOC and IP blocks to ensure design intent.
• Perform RTL verification using industry-standard methodologies like UVM and SystemVerilog.
• Collaborate with design engineers to address complex debug issues and optimize strategies.
• Work closely with customer and internal engineering teams to provide high-quality support.
• Participate in coverage analysis, regression testing, and verification goal closure.
• Contribute to the development of reusable verification environments and testbenches.

Requirements

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 3–5 years of hands-on experience in VLSI/SOC design verification.
• Strong expertise in SystemVerilog, UVM, and industry-standard verification tools.
• Experience with protocols such as AMBA, PCIe, USB, MIPI, or DDR/LPDDR.
• Ability to bridge communication between local teams and global stakeholders.

Nice to have

• Experience with ARM or RISC-V processor integration.