Memory Validation Architect (FPGA)

Location: San Jose, California, United States. Onsite role; applicants must be eligible for required U.S. export authorizations.

Salary: $209,500–$303,000 USD annually for the Bay Area California location.

Company

hirify.global is a pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Define and own validation architecture and strategy for memory subsystems across multiple FPGA product families.
• Lead validation planning from architecture definition through silicon bring-up, characterization, qualification, and customer deployment.
• Build scalable validation frameworks, reusable infrastructure, automation, metrics, dashboards, and AI-driven debug methodologies.
• Lead pre-silicon and post-silicon validation for DDR5, LPDDR5/LPDDR6, HBM, memory controllers, PHYs, and training and calibration algorithms.
• Drive functional, performance, margining, reliability, stress, error-recovery, compliance, and interoperability validation.
• Investigate complex issues across RTL, firmware, board design, signal integrity, package interactions, and system software while mentoring engineers and influencing future architectures.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 15+ years of industry experience; equivalent requirements apply for master’s or doctoral degrees.
• 10+ years of hands-on experience designing, validating, debugging, or optimizing DDR memory technologies, including DDR4, DDR5, LPDDR4, LPDDR5, HBM, or newer JEDEC standards.
• 10+ years of experience across memory controller or DDR PHY architecture, memory initialization and training, calibration algorithms, JEDEC specifications, or memory timing analysis.
• 8+ years leading or contributing to silicon bring-up, debug, characterization, validation, and production qualification for complex SoCs or memory subsystems.
• 8+ years of board-level signal integrity, power integrity, timing analysis, or high-speed memory channel validation experience.
• 5+ years using high-speed laboratory equipment and programming or automation tools such as Python or C/C++.

Nice to have

• FPGA or ASIC memory subsystem development experience.
• Expertise in HBM, CXL Memory, Compute Express Link, or emerging memory technologies.
• Experience with Micron, Samsung, or SK hynix and with PCIe, CXL, AXI, AMBA, or coherent interconnect architectures.
• Experience defining organization-wide validation methodologies and leading globally distributed engineering teams.

Culture & Benefits

• Opportunity to influence FPGA product architecture and validation strategy across multiple generations.
• Collaboration with architecture, RTL, firmware, board design, signal integrity, software, product engineering, customers, and DRAM vendors.
• Regular employment with incentive opportunities based on individual and company performance.