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23 часа назад

Senior Compiler Engineer (C++)

160 000 - 210 000$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Compiler Engineer (C++/ML): Developing compiler features and embedded machine-learning applications for an energy-efficient programmable processor with an accent on dataflow ISA support, memory analysis, hardware-aware optimization, and ML framework integration. Focus on compiling models to custom hardware, debugging functional and performance issues, and designing tests and tools for complex hardware constraints.

Location: San Jose, California; Pittsburgh, Pennsylvania; or the San Francisco Bay Area, United States

Salary: $160,000–$210,000 per year, plus equity and comprehensive benefits

Company

hirify.global develops an energy-efficient general-purpose processor designed to enable continuous machine learning and intelligence in IoT devices.

What you will do

  • Design and implement compiler features for Efficient’s dataflow instruction set architecture.
  • Improve hardware efficiency through memory analysis and ordering, timing and power optimization, and place-and-route of applications.
  • Develop visualization and programmer debugging tools.
  • Compile machine-learning models from multiple frameworks for custom hardware and build TinyML applications.
  • Write unit and integration tests and debug functional and performance issues.
  • Collaborate with hardware, physical design, and application development teams to improve compiler and processor architecture.

Requirements

  • 6+ years of professional C++ experience.
  • Bachelor’s or master’s degree in computer science or a related field.
  • Familiarity with GCC, LLVM, and/or MLIR compiler frameworks.
  • Understanding of computer architecture and optimization.
  • Experience with development and debugging tools, including GDB.
  • Strong problem-solving, communication, attention-to-detail, and multitasking skills.

Nice to have

  • Familiarity with FPGA compilation and/or place-and-route algorithms.
  • Experience with Verilog, SystemVerilog, or VHDL.
  • Additional knowledge of computer architecture.

Culture & Benefits

  • Meaningful equity program.
  • 401(k) match and company-paid benefits.
  • Paid parental leave.
  • Flexible work arrangements.
  • Support for personal and professional development.

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