21 час назад
IP Design Verification Engineer (DDR5/LPDDR5)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
IP Design Verification Engineer (DDR5/LPDDR5): Validating complex IP architectural and microarchitectural features across RTL and gate-level simulation environments with an accent on SystemVerilog, UVM, protocol compliance, and coverage-driven verification. Focus on debugging simulation failures, verifying asynchronous and multi-cycle paths, automating pre-silicon validation flows, and integrating IP with system and SoC teams.
Location: Penang, Malaysia; hybrid work model with time split between the assigned site and off-site work
Company
develops computing technologies and IP designs for advanced semiconductor products.
What you will do
- Own RTL validation for functional and design-for-test/debug features.
- Define verification strategies, methodologies, and detailed test plans.
- Create Bus Functional Models, monitor transactions, and verify protocol compliance.
- Implement test cases, assertions, and functional coverage using SystemVerilog.
- Set up gate-level simulations, debug RTL and GLS failures, and analyze coverage gaps.
- Collaborate with architects, RTL developers, physical design teams, and system and SoC teams on IP integration.
Requirements
- Bachelor’s or advanced degree in Electrical Engineering, Computer Engineering, or a related discipline.
- At least 6 years of experience with a Bachelor’s degree, 4 years with a Master’s degree, or 2 years with a PhD.
- Strong proficiency in SystemVerilog and verification methodologies including OVM and UVM.
- Expertise in DDR protocols, particularly LPDDR5 and DDR5, covering validation from specifications through coverage.
- Experience with RTL validation, logic design, DFx concepts, IP microarchitecture debugging, and tools such as VCS, DVE, or Verdi.
- Familiarity with UNIX environments, shell scripting, and C programming.
Nice to have
- Experience resolving formal verification challenges and debugging complex simulation failures.
- Proficiency in Tcl, Tk, Perl, and Python for verification automation.
- Strong communication skills for collaboration with cross-functional teams and global partners.
Culture & Benefits
- Hybrid work model combining on-site work at the assigned site with off-site work.
- Full-time employment as an experienced hire.
- Regular Shift 1 schedule in Malaysia.
- Commitment to ethical hiring and responsible business practices; no recruitment or employment-related fees are charged.
Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →
Похожие вакансии
9 часов назад
FPGA Silicon Design Verification Engineer (FPGA)
6 дней назад
Test Engineer (NPI Development)
10 часов назад
Associate Quality Assurance Engineer (SSD)
7 часов назад
Quality Engineer, Professional Senior (ISO 9001)
7 часов назад
Intern, Support II (Software Testing)
8 часов назад