Senior Density Fill Development Engineer (Semiconductor)

Location: Hybrid work model with on-site and off-site work at an assigned hirify.global site in the United States; primary location Hillsboro, Oregon, with additional locations in Phoenix, Arizona; Santa Clara, California; and Austin, Texas.

Salary: $128,880–$245,160 annual USD

Company

hirify.global develops semiconductor technologies, hardware products, and design automation solutions.

What you will do

• Design, develop, test, and debug density fill components for process design kits.
• Develop algorithmic solutions with Calibre, ICV, and Pegasus to address density deficiencies and manufacturability requirements.
• Collaborate with process developers, design rule owners, end users, and external EDA vendors to define requirements and implement tool features.
• Automate workflows and develop test systems to improve efficiency, accuracy, deployment, and integration with design methodologies.
• Advance EDA tools and methodologies for evolving semiconductor process technologies.
• Maintain documentation, training materials, and user guides for customers and design teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience; alternatively, a master’s degree with 5+ years or a PhD with 2+ years.
• At least 5 years of hands-on experience with Calibre, ICV, or Pegasus, including methodology development, rule-deck debugging, or production deployment.
• At least 3 years of experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, PVL, or PVTCL.
• Strong understanding of semiconductor device physics, process technology, design rules, and advanced-node physical design challenges.
• Strong knowledge of Unix/Linux platforms and computing environments.
• Ability to work in a hybrid model with on-site work at an assigned hirify.global location in the United States.

Nice to have

• 5+ years of experience with density fill methodologies for semiconductor technologies at 16nm and below.
• Experience with advanced physical verification, DRC, density, and fill modules.
• Experience with foundry technologies, advanced packaging organizations, IDMs, or EDA vendors.
• Familiarity with Cadence Virtuoso or Synopsys Custom Designer.
• Leadership experience in innovation, process improvement, or cross-functional initiatives.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Competitive pay and stock bonuses.
• Health, retirement, and vacation benefits.
• Cross-functional collaboration with internal teams and external EDA vendors.