3 Π΄Π½Ρ Π½Π°Π·Π°Π΄
ASIC Verification Engineer (SoC)
ΠΡΡΡ & Π‘ΠΎΠΏΡΠΎΠ²ΠΎΠ΄
ΠΠ»Ρ ΠΌΡΡΡΠ° Ρ ΡΡΠΎΠΉ Π²Π°ΠΊΠ°Π½ΡΠΈΠ΅ΠΉ Π½ΡΠΆΠ΅Π½ Plus
ΠΠΏΠΈΡΠ°Π½ΠΈΠ΅ Π²Π°ΠΊΠ°Π½ΡΠΈΠΈ
Π’Π΅ΠΊΡΡ:
TL;DR
ASIC Verification Engineer (SoC): Developing and verifying ARTPEC SoC hardware modules for network video and surveillance products with an accent on software-driven SoC verification, constrained-random verification, and digital design concepts. Focus on building SystemVerilog and UVM verification environments, applying formal and low-power verification methodologies, and validating complex protocols and hardware-software interactions.
Location: Sweden, Stockholm
Company
develops network video, access control, intercom, and audio solutions with intelligent analytics for security and business performance.
What you will do
- Develop, implement, integrate, and verify ASIC hardware modules for ARTPEC SoC chips used in surveillance cameras.
- Perform software-driven, SoC-level verification of interconnect fabrics, protocols, and essential IP components.
- Build coverage-driven constrained-random verification environments for modules and subsystems.
- Apply SystemVerilog and UVM to verify digital designs involving RTL, finite-state machines, pipelines, clocking, and resets.
- Investigate new verification methodologies and contribute to study circles, workshops, documentation, and continuous improvement.
- Collaborate with junior and senior engineers to solve technical challenges and share knowledge.
Requirements
- Bachelorβs or masterβs degree in electrical engineering, computer science, engineering physics, or a similar field.
- Professional experience with SoC-level verification, software-driven verification, interconnect fabrics, and protocols.
- Experience with coverage-driven constrained-random verification using SystemVerilog and UVM.
- Strong understanding of digital design concepts, including RTL, FSMs, pipelines, clocking, and resets.
- Proficiency in SystemVerilog, Python, C, C++, and SystemC.
- Strong analytical, problem-solving, communication, and teamwork skills.
Nice to have
- Experience with formal verification, assertion-based methodologies, low-power verification using UPF or CPF, and transaction-level modeling.
- Knowledge of AXI, PCIe, Ethernet, or DDR protocols.
- Experience with gate-level simulation, post-silicon validation, embedded systems, and hardware-software interactions.
- Ability to create structured and well-organized technical documentation.
Culture & Benefits
- Collaborative, open, and technology-focused R&D environment in a new central Stockholm office.
- Continuous learning through workshops, study circles, and knowledge sharing.
- Company bonus, wellness allowance, health insurance, and an Axis bicycle.
- Work-life balance, professional development, and participation in projects with global security and surveillance impact.
Hiring process
- Recruitment contact: Hans RΓΆnne, Recruiting ASIC Platform Manager.
- Some roles may require background checks; applicants will be notified before any verification is conducted.
ΠΡΠ΄ΡΡΠ΅ ΠΎΡΡΠΎΡΠΎΠΆΠ½Ρ: Π΅ΡΠ»ΠΈ ΡΠ°Π±ΠΎΡΠΎΠ΄Π°ΡΠ΅Π»Ρ ΠΏΡΠΎΡΠΈΡ Π²ΠΎΠΉΡΠΈ Π² ΠΈΡ ΡΠΈΡΡΠ΅ΠΌΡ, ΠΈΡΠΏΠΎΠ»ΡΠ·ΡΡ iCloud/Google, ΠΏΡΠΈΡΠ»Π°ΡΡ ΠΊΠΎΠ΄/ΠΏΠ°ΡΠΎΠ»Ρ, Π·Π°ΠΏΡΡΡΠΈΡΡ ΠΊΠΎΠ΄/ΠΠ, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡΠ΅ ΡΡΠΎΠ³ΠΎ - ΡΡΠΎ ΠΌΠΎΡΠ΅Π½Π½ΠΈΠΊΠΈ. ΠΠ±ΡΠ·Π°ΡΠ΅Π»ΡΠ½ΠΎ ΠΆΠΌΠΈΡΠ΅ "ΠΠΎΠΆΠ°Π»ΠΎΠ²Π°ΡΡΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡΠΈΡΠ΅ Π² ΠΏΠΎΠ΄Π΄Π΅ΡΠΆΠΊΡ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β
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