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3 дня назад

ASIC Verification Engineer (SoC)

Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
Sweden
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR
ASIC Verification Engineer (SoC): Developing and verifying ARTPEC SoC hardware modules for network video and surveillance products with an accent on software-driven SoC verification, constrained-random verification, and digital design concepts. Focus on building SystemVerilog and UVM verification environments, applying formal and low-power verification methodologies, and validating complex protocols and hardware-software interactions.

Location: Sweden, Stockholm

Company

hirify.global develops network video, access control, intercom, and audio solutions with intelligent analytics for security and business performance.

What you will do

  • Develop, implement, integrate, and verify ASIC hardware modules for ARTPEC SoC chips used in surveillance cameras.
  • Perform software-driven, SoC-level verification of interconnect fabrics, protocols, and essential IP components.
  • Build coverage-driven constrained-random verification environments for modules and subsystems.
  • Apply SystemVerilog and UVM to verify digital designs involving RTL, finite-state machines, pipelines, clocking, and resets.
  • Investigate new verification methodologies and contribute to study circles, workshops, documentation, and continuous improvement.
  • Collaborate with junior and senior engineers to solve technical challenges and share knowledge.

Requirements

  • Bachelor’s or master’s degree in electrical engineering, computer science, engineering physics, or a similar field.
  • Professional experience with SoC-level verification, software-driven verification, interconnect fabrics, and protocols.
  • Experience with coverage-driven constrained-random verification using SystemVerilog and UVM.
  • Strong understanding of digital design concepts, including RTL, FSMs, pipelines, clocking, and resets.
  • Proficiency in SystemVerilog, Python, C, C++, and SystemC.
  • Strong analytical, problem-solving, communication, and teamwork skills.

Nice to have

  • Experience with formal verification, assertion-based methodologies, low-power verification using UPF or CPF, and transaction-level modeling.
  • Knowledge of AXI, PCIe, Ethernet, or DDR protocols.
  • Experience with gate-level simulation, post-silicon validation, embedded systems, and hardware-software interactions.
  • Ability to create structured and well-organized technical documentation.

Culture & Benefits

  • Collaborative, open, and technology-focused R&D environment in a new central Stockholm office.
  • Continuous learning through workshops, study circles, and knowledge sharing.
  • Company bonus, wellness allowance, health insurance, and an Axis bicycle.
  • Work-life balance, professional development, and participation in projects with global security and surveillance impact.

Hiring process

  • Recruitment contact: Hans RΓΆnne, Recruiting ASIC Platform Manager.
  • Some roles may require background checks; applicants will be notified before any verification is conducted.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’