Physical Design Methodology Engineer (AI)

Company

hirify.global is a hardware startup building frontier inference clusters for AI, co-designing chips, racks, and software to redefine the infrastructure layer for the fastest-growing industry in history.

What you will do

• Architect, build, and maintain automated RTL-to-GDSII flows from synthesis to signoff.
• Develop and own CAD infrastructure, including tool version qualification and compute resource management.
• Create and maintain block-level and full-chip PG mesh and floorplanning flows.
• Drive PPA tuning and timing correlation across pre-route, post-route, and signoff environments.
• Partner with design owners to debug flow issues and implement methodology-level fixes.

Requirements

• 5-10+ years of experience in Physical Design or PD methodology/CAD.
• Strong proficiency in Tcl and Python for flow development and automation.
• Experience with automated RTL-to-GDSII flows using Cadence (Innovus, Genus) or Synopsys (Fusion Compiler).
• Deep understanding of advanced process nodes (5nm and below) and UPF-based low-power design.
• Must be based in or willing to relocate to San Jose, CA (on-site role).

Nice to have

• Startup experience or comfort in fast-paced environments.
• Familiarity with modern ML/LLM architectures and AI tools for programming.
• Experience with compute farm and job scheduler optimization for EDA workloads.

Culture & Benefits

• Medical, dental, and vision packages with generous premium coverage.
• Housing subsidy of $2k per month for those living within walking distance of the office.
• Relocation support for those moving to San Jose.
• Daily lunch and dinner provided in the office.
• Unlimited compute budget subject to ROI justification.