Asic Design Engineer

TL;DR

Asic Design Engineer: Develops high performance connectivity silicon that underpins AI scale data centers for the world’s leading hyperscalers with an accent on digital pipelines, high speed datapaths, and DSP driven processing engines. Focus on shaping foundational connectivity technologies and contributing to silicon solutions powering the global AI infrastructure.

Location: Irvine, CA Austin, TX US-NY - Hudson Valley Santa Clara, CA US-VA - Dulles

Salary: 151,000 - 223,440 USD per annum

Company

hirify.global’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.

What you will do

• Collaborate with systems and architecture teams to define SoC‑level specifications.
• Translate high‑level product and protocol requirements into detailed micro‑architecture specifications.
• Own RTL development for assigned blocks, delivering high‑quality, synthesizable SystemVerilog RTL.
• Implement and drive the full ASIC front‑end design flow.
• Partner with STA and PNR teams to support timing closure, floorplanning, congestion analysis, and design optimizations.
• Drive post‑silicon bring‑up and debug, collaborating with lab and systems teams.

Requirements

• Extensive experience in digital ASIC design, including micro‑architecture development, RTL implementation (SystemVerilog preferred), and integration of complex logic blocks.
• 10+ years of industry experience working on large‑scale ASICs for networking, data‑center connectivity, or high‑bandwidth compute architectures.
• Strong background in high‑performance DSP and high‑speed datapath design.
• Familiarity with Ethernet protocols and networking standards.
• Proficiency with front‑end design flows.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.

Nice to have

• Advanced high‑speed DSP algorithm implementation.
• Experience with FEC architectures such as LDPC, RS, BCH, or other high‑speed coding/decoding schemes used in networking and optical interconnects.
• Previous PHY design experience, including PMA‑level DSP pipelines, equalization blocks, clock recovery, and SerDes‑adjacent logic.

Culture & Benefits

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.