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2 дня назад

Computer Architect (AI Accelerators)

200 000 - 265 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Computer Architect (AI Accelerators): Designing and optimizing next-generation chip architectures for AI inference workloads with an accent on throughput, latency, power efficiency, and architectural modeling. Focus on defining compute-block interfaces, running cycle-accurate simulations, and solving cross-functional challenges from architecture through silicon.

Location: On-site in San Jose, California; relocation support is available for candidates moving to San Jose.

Salary: $200,000–$265,000 per year plus significant equity.

Company

hirify.global develops hardware, software, racks, and manufacturing systems for frontier AI inference, with a focus on high throughput and low latency.

What you will do

  • Design and analyze chip architectures optimized for AI and machine learning workloads.
  • Develop power and area estimation methodologies for early-stage architectural exploration.
  • Create architectural specifications and interface definitions for compute blocks and subsystems.
  • Collaborate with RTL, verification, physical design, and software teams to validate and optimize chip designs.
  • Run architectural experiments using cycle-accurate simulators and analytical performance models.
  • Support integration by providing architectural guidance and resolving design challenges.

Requirements

  • PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in computer architecture, ASIC design, or related fields.
  • Strong knowledge of pipelines, memory hierarchies, interconnects, processor microarchitecture, and design tradeoffs.
  • Experience with performance modeling and architectural simulation tools.
  • Hands-on experience designing and optimizing floating-point datapaths or arithmetic-intensive circuits with advanced process nodes.
  • Proficiency in Rust, C/C++, or Python, plus strong analytical, problem-solving, and communication skills.

Nice to have

  • Experience with AI/ML accelerator architectures, dataflow optimization, RTL design and verification, or cycle-accurate simulation tools such as gem5 and SystemC.
  • Knowledge of power and performance analysis, ASIC design flows, physical design constraints, tapeout, or silicon bring-up.
  • Publications or presentations at architecture conferences such as ISCA, MICRO, or HPCA.

Culture & Benefits

  • Fully in-person engineering and research environment in San Jose.
  • Medical, dental, and vision coverage, plus a $500 monthly credit for waiving medical benefits.
  • $2,000 monthly housing subsidy for employees living within walking distance of the office.
  • Relocation support, wellness benefits, and daily lunch and dinner at the office.
  • Unlimited compute budget subject to return-on-investment justification.

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