1 день назад
HSIO Test Solutions Engineering Lead (SerDes)
138 400 - 204 800$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
HSIO Test Solutions Engineering Lead (SerDes): Defining test strategies, DFT requirements, silicon validation, and manufacturing test plans for next-generation SerDes, chiplet, and die-to-die semiconductor products with an accent on testability, observability, diagnostics, and high-volume manufacturing readiness. Focus on characterizing high-speed interfaces across voltage, frequency, and temperature conditions, correlating validation with production requirements, and improving quality, yield, and test efficiency.
Location: Irvine, CA, United States
Salary: $138,400–$204,800 per annum, plus eligibility for bonus and equity plans.
Company
develops semiconductor solutions that support enterprise, cloud, AI, carrier, networking, and data infrastructure applications.
What you will do
- Develop test strategies and DFT requirements for advanced HSIO, SerDes, chiplet, and die-to-die technologies.
- Influence product testability, observability, and diagnostic capabilities during architecture and design.
- Define and execute test-chip and first-silicon validation strategies, including characterization across voltage, frequency, and temperature conditions.
- Develop production screening methodologies and manufacturing test plans for production deployment.
- Analyze production data and drive improvements in product quality, yield, and test efficiency.
- Lead cross-functional technical reviews, influence decisions, mentor engineers, and collaborate with design, validation, product engineering, reliability, and manufacturing teams.
Requirements
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a related field.
- 10+ years of experience in semiconductor Test Engineering, Product Engineering, DFT, Silicon Validation, or related disciplines.
- Strong understanding of semiconductor manufacturing, yield analysis, and qualification methodologies.
- Experience with one or more of: high-speed SerDes, PCIe, CXL, UCIe, die-to-die interfaces, DFT, silicon validation and debug, ATE, production test development, or mixed-signal characterization.
- Demonstrated ability to lead complex cross-functional technical initiatives.
- Applicants must be eligible to access technology and software subject to U.S. export control laws; an export license review may be required.
Nice to have
- MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience with Advantest 93K or Teradyne UltraFLEX platforms.
- Experience with advanced packaging, chiplets, heterogeneous integration, or AI, networking, cloud, and data center products.
- Experience with Python, automation, analytics, or test infrastructure development.
Culture & Benefits
- Full-time employment with eligibility for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
- Employee stock purchase plan with a two-year lookback.
- Family support programs and resources for balancing work and home life.
- Mental and physical health resources, including mental health support.
- Recognition and service awards.
Hiring process
- Interviews are designed to evaluate individual experience, thought process, and communication skills in real time.
- AI tools, transcription applications, automated answer generators, and automated note-taking bots are not permitted during interviews.
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