Design Verification Tech Lead (SerDes/PHY IP)

Location: San Jose, California, United States

Salary: $160,000–$200,000 per year, depending on experience, level, and business need. Discretionary bonus, incentives, and benefits may also apply.

Company

hirify.global develops connectivity solutions for rack-scale AI infrastructure, integrating CXL, Ethernet, NVLink, PCIe, UALink, and software technologies.

What you will do

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, sign-off criteria, and methodology across co-simulation, gate-level simulation, and emulation flows.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
• Verify equalization, CDR, training, link bring-up, channel behavior, and physical-layer state machines across PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet standards.
• Drive coverage closure, debug failures with designers, and manage regressions through tape-out.
• Mentor design verification engineers and collaborate with analog/mixed-signal, SoC integration, firmware, post-silicon validation, and customer engineering teams.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of design verification experience with high-speed SerDes, PHY, or mixed-signal IP.
• Expert-level SystemVerilog and UVM proficiency.
• Strong understanding of equalization, CDR, training sequences, link bring-up, and physical-layer behavior.
• Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling.
• Working knowledge of PCIe, UALink, UCIe, Ethernet, or CXL.

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering.
• Experience with PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
• Familiarity with Palladium, Veloce, ZeBu, and gate-level simulation flows.
• Python or Perl scripting for verification automation and regression management.
• Post-silicon bring-up experience and the ability to lead technical work across multidisciplinary teams.

Culture & Benefits

• Work on connectivity technologies supporting advanced AI platforms.
• Collaborate across analog, digital, SoC, firmware, validation, and customer engineering functions.
• Discretionary bonus, incentives, and benefits may be available.
• Applications are encouraged from candidates with diverse backgrounds and experiences.