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Principal SoC Architect (AI)

300Β 000 - 350Β 000$
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

ОписаниС вакансии

ВСкст:
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TL;DR
Principal SoC Architect (AI): Leading end-to-end architecture for advanced AI inference chips with an accent on performance, power, cost, and system-level efficiency. Focus on designing memory subsystems, high-speed interconnects, control paths, chiplet integration, silicon bring-up, and cross-functional execution from architecture through production.

Location: Santa Clara County, California, United States

Salary: $300,000–$350,000 per year

Company

Early-stage AI infrastructure startup backed by Tier-1 venture capital firms, developing chips and systems for highly efficient inference workloads.

What you will do

  • Lead end-to-end SoC architecture for next-generation AI inference chips.
  • Define key SoC blocks, interfaces, and architectural trade-offs across performance, power, area, schedule, and cost.
  • Architect PCIe Gen5-or-higher connectivity, scale-up and scale-out interconnects, and UCIe integration.
  • Design HBM and LPDDR memory subsystems, including bandwidth modeling and memory controller integration.
  • Define CPU complex, boot flows, security, power, reset, and clocking control paths.
  • Coordinate with RTL, firmware, validation, packaging, and bring-up teams through silicon debug and performance tuning.

Requirements

  • Experience architecting real, shipping SoCs across the full development lifecycle.
  • Strong knowledge of SoC blocks and their interfaces, including architecture, RTL, firmware, and bring-up workflows.
  • Experience with PCIe Gen5 or higher, scale-up or scale-out interconnects, and UCIe.
  • Experience with HBM or LPDDR memory architecture, bandwidth modeling, and memory controller integration.
  • Experience designing CPU control paths, boot flows, security, power, reset, and clocking systems.
  • Experience with silicon bring-up, debug strategy, and performance optimization.

Nice to have

  • Early-stage SoC development experience in a startup environment.
  • Chiplet or multi-die SoC experience.
  • Experience with AI accelerators, GPUs, or high-bandwidth networking silicon.

Culture & Benefits

  • Opportunity to make a substantial impact on a fundamentally new chip and system architecture.
  • Work on AI infrastructure innovation at both the chip and system levels.
  • Build products from the ground up in an early-stage startup environment.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’