CPU Physical Design Engineer

TL;DR

CPU Physical Design Engineer (CPU physical design/EDA): Implementing custom CPU designs from RTL to GDS for advanced client, server, and AI processors with an accent on timing closure, power efficiency, reliability, and manufacturability. Focus on optimizing physical design flows, resolving complex timing and power integrity challenges, and collaborating with architecture, circuit, logic, design automation, and EDA vendor teams.

Location: On-site in Austin, Texas, United States.

Annual salary: $105,650–$149,150 USD.

Company

hirify.global develops semiconductor technologies and compute processors spanning client, server, AI, analytics, and cloud-to-edge applications.

What you will do

• Implement custom CPU physical designs from RTL through GDS, producing manufacturing-ready design databases.
• Execute synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, power distribution, reliability, and power and noise analysis.
• Perform formal equivalence, timing, power integrity, layout, electrical rule, structural, DRC/LVS, and other signoff verification.
• Analyze verification results and recommend improvements to CPU microarchitecture, timing, power, frequency, and area.
• Develop and improve physical design methodologies, flow automation, and EDA tool capabilities with industry vendors.
• Collaborate with logic, circuit, architecture, clocking, full-chip design, and design automation teams.

Requirements

• Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related field with 2+ years of relevant experience, or a master’s degree with 1+ years of relevant experience.
• At least 1 year of experience synthesizing a digital logic block or partition.
• At least 1 year of experience with Synopsys or Cadence tools, logic synthesis, place and route, static timing analysis, and design closure.
• Experience with PV convergence, power analysis, formal equivalence, electrical rules, DRC/LVS, noise flow, and TCL scripting.
• Experience or knowledge in floor planning, routing, clock distribution, RTL-to-GDS methodologies, timing constraints, and reliability verification.
• On-site presence in Austin, Texas, United States is required.

Nice to have

• Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
• At least one completed tape-out on advanced technology.
• CPU-level timing analysis and optimization experience.
• Experience balancing timing fixes, power delivery, clocking, and partitioning with clocking and full-chip design teams.

Culture & Benefits

• Work on advanced CPU and semiconductor technologies across client, server, and AI products.
• Competitive compensation with stock bonuses.
• Health, retirement, vacation, and other employee benefit programs.
• Shift 1 work schedule with on-site presence.