Staff Layout Engineer (IC Layout)

TL;DR

Staff Layout Engineer (IC Layout): Developing and verifying memory, I/O, and standard-cell layouts for advanced CMOS technologies with an accent on physical verification, floor-planning, and chip integration. Focus on applying complex process rules, completing LVS/DRC/ERC verification, and leading methodology reviews and junior engineer development.

Location: Shanghai, China; the position is stationed in Singapore, and relocation to Singapore is required immediately.

Company

hirify.global develops semiconductor and infrastructure technology products, including advanced integrated-circuit solutions.

What you will do

• Design and deliver memory, I/O, and standard-cell layouts for advanced CMOS processes.
• Apply layout guidelines, process rules, and technical requirements to ensure high-quality implementation.
• Plan layout floor-plans, schedules, hierarchy, and chip integration activities.
• Complete physical verification within planned timelines using LVS, DRC, ERC, antenna, and electromigration checks.
• Review new technologies and document layout methodologies, flows, and guidelines.
• Lead or train junior engineers while collaborating independently and within the library team.

Requirements

• At least 8 years of IC layout experience.
• Strong experience with memory layout design, topology, and physical verification in CMOS processes.
• Experience with Cadence Layout and Virtuoso XL, VXL, or EXL, plus Calibre verification tools; familiarity with Hercules is required.
• Experience with submicron processes such as 16nm, 7nm, 5nm, 2nm, A14, or below.
• Experience with floor-planning, hierarchical layout, and chip integration.
• Must be available to relocate to Singapore immediately.

Nice to have

• Analog layout experience.
• Memory compiler experience.
• Script programming and SKILL programming knowledge.
• Strong leadership and project management skills.

Culture & Benefits

• Work independently and collaboratively within the Library Group.
• Contribute to Central Engineering Group methodologies and technical documentation.
• Equal opportunity employment regardless of protected characteristics.