Lead Design Engineer (Virtual Solution)

TL;DR

Lead Design Engineer (Virtual Solution): Design and develop system-level AVIP solutions for emulation and prototyping platforms with an accent on SoC and subsystem validation. Focus on building end-to-end verification flows, optimizing emulation efficiency, and implementing custom test cases for complex hardware systems.

Location: Must be based in Shanghai

Company

hirify.global is a leading provider of electronic design automation (EDA) software and hardware tools for the semiconductor and electronics industries.

What you will do

• Design and develop system-level AVIP solutions for Palladium and Protium emulation/prototyping platforms.
• Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation.
• Develop end-to-end verification flows, including testbench and system modeling.
• Optimize solutions for performance, scalability, and emulation efficiency.
• Create custom test cases and automation tools to enable advanced embedded and hybrid flows.
• Collaborate with cross-functional teams and customers to debug and resolve system-level issues.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of relevant professional experience.
• Strong expertise in high-speed protocols such as PCIe, CXL, AMBA, UCIe, or Ethernet.
• Proficiency in RTL design (SystemVerilog/Verilog) and C/C++ development.
• English: C1 (excellent) communication skills are required.
• Location: Position is based in Shanghai.

Nice to have

• Experience developing or using AVIP solutions and knowledge of UVM frameworks.
• Knowledge of Qemu, Gem5, or other system emulation projects.
• Experience with multi-language environments (SystemVerilog, C/C++, and Python).
• Exposure to AI/ML techniques applied to verification or tooling.