Principal Package Signal & Power Integrity Engineer

Location: San Jose, California, United States

Base salary: $203,000–$240,000 USD per year

Company

hirify.global provides rack-scale AI infrastructure through semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, UALink, and the COSMOS software suite.

What you will do

• Architect, optimize, and sign off package signal and power integrity solutions for high-performance connectivity products.
• Lead SIPI strategy for PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnects.
• Perform package and system-level simulations using HFSS, SIwave, Keysight ADS, and equivalent tools.
• Drive chip–package–board co-design across silicon, SerDes/IP, package, PCB, validation, manufacturing, substrate, and OSAT teams.
• Correlate EM models and system simulations with VNA, TDR, and high-speed oscilloscope measurements.
• Establish modeling standards, routing guidelines, automation flows, signoff methodologies, and mentorship practices.

Requirements

• 10+ years of experience in signal integrity, power integrity, package electrical design, or chip–package–board co-design for high-performance semiconductor products.
• Deep expertise in package SIPI modeling, analysis, optimization, and signoff for high-speed SerDes, PCIe, CXL, and Ethernet.
• Experience with PAM4 SerDes, S-parameter extraction, package model development, eye-diagram analysis, loss optimization, and crosstalk analysis.
• Hands-on experience with EM extraction and SIPI tools such as ANSYS HFSS, SIwave, Q3D, 3D Layout, Keysight ADS, or Cadence Sigrity.
• Expert knowledge of PDN design, including IR drop, AC impedance, loop inductance, decoupling, transient response, noise coupling, and chip-package-model methodology.
• Experience correlating simulations with lab measurements and leading vendor engagements through production ramps.

Nice to have

• Experience with silicon floor planning, bump maps, SerDes and power-grid planning, package escape, and PCB breakout.
• Automation and scripting experience for SIPI modeling flows.
• Exposure to Allegro Package Designer and advanced package manufacturing processes.
• Experience with CPO and NPO optical package SIPI design and optical connectivity applications.

Culture & Benefits

• Work involves collaboration with hyperscalers, ecosystem partners, internal engineering teams, substrate vendors, and OSAT partners.
• The role balances SIPI performance, cost, manufacturability, reliability, yield, and schedule.
• hirify.global encourages applications from candidates with diverse backgrounds and experiences.