R&D Engineer IC Design (Optical Communication)

TL;DR

R&D Engineer IC Design (Optical Communication): Designing and architecting block-level specifications for chips enabling Physical Layer Products for high-speed optical communication with an accent on RTL coding and silicon validation. Focus on optimizing leakage, dynamic power, and die size while ensuring system reliability for Ethernet and OTN networks.

Location: Onsite in San Jose, CA, USA

Salary: $143,800 – $230,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Architect block level design specifications based on marketing and system requirements.
• Perform RTL coding, Lint checks, CDC, Synthesis, and STA.
• Conduct RTL/gate level simulations, silicon debug, and ATE program bring-up.
• Develop scripts for IC design tasks using Python, Perl, or C.
• Execute design tradeoff analysis focusing on power, leakage, and die size.
• Create verification and test plans for design validation.

Requirements

• B.S. in EE or Computer Engineering (12+ years exp) or M.S./Ph.D. (10+ years exp).
• Must be located in or authorized to work in the USA (San Jose, CA).
• Deep knowledge of high-speed digital circuit design and ARM subsystems.
• Expertise in 10G to 800G Ethernet and OTN networks.
• Proficiency in Verilog, VHDL, and scripting languages (Python/Perl).
• Strong understanding of FEC (Forward Error Correction) and digital signal processing.

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(K) with company matching and Employee Stock Purchase Program (ESPP).
• Discretionary annual bonus and competitive equity grants.
• Paid sick leave, vacation time, and company-paid holidays.
• Equal opportunity employer committed to diversity and inclusion.