Layout Engineer (Semiconductors)

TL;DR

Layout Engineer (Semiconductors): Developing circuit layouts for memory, I/O, and standard cells with an accent on submicron processes and physical verification. Focus on floor-planning, hierarchy layout, and ensuring DRC/LVS compliance using Cadence and Calibre tools.

Location: Singapore (Yishun)

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Apply layout guidelines and new process rules for standard cells, I/O, and memory layout.
• Manage layout floor-planning and define schedule timelines.
• Execute high-quality layout and verification independently.
• Perform physical verifications including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
• Collaborate with the library team to implement new methodologies and documentation.
• Lead and train junior engineers on layout topology and project management.

Requirements

• 3 to 4 years of experience in layout engineering.
• Proficiency with Cadence layout, schematic capture, CALIBRE, and Hercules verification tools.
• Strong knowledge of submicron processes (e.g., 16nm, 7nm, 5nm, 3nm, 2nm, 1.4nm).
• Experienced in digital layout for standard cells, memory, and I/O.
• Must be located in or authorized to work in Singapore.

Nice to have

• Experience in analog layout.
• Knowledge of Script Programming and SKILL Programming.
• Experience with memory compilers.