Senior Principal DFT Design Engineer

TL;DR

Senior Principal DFT Design Engineer (DFT/SoC-ASIC): Developing and optimizing Design for Test (DFT) flows for SoC/ASIC, with an accent on scan chain insertion, compression scan technologies, MBIST, and systematic ATPG pattern generation. Focus on achieving design test coverage goals, debugging ATPG failures and simulation mis-compares, and validating DFT testbenches with strong problem-solving across cross-functional stakeholders.

Location: Austin

Company

hirify.global develops technology solutions for the semiconductor and electronics design ecosystem.

What you will do

• Own DFT insertion flows for SoC/ASIC, including scan chain insertion and related tooling flows.
• Implement and optimize compression scan insertion, LBIST, and other scan technologies.
• Develop and drive MBIST expertise to support memory test coverage.
• Generate ATPG patterns to meet design test coverage goals using systematic quality metrics.
• Debug and analyze failures to improve fault coverage, including root-cause analysis of simulation mis-compares.
• Verify ATPG testbenches and collaborate with cross-functional stakeholders (architecture, design, internal and external customers).

Requirements

• 10–20 years of professional experience in SoC/ASIC digital design with a focus on Design for Test (DFT).
• Deep knowledge of DFT insertion flows and scan chain insertion (including using synthesis or other software tools).
• Hands-on expertise with compression scan insertion, LBIST and related scan technologies.
• In-depth knowledge of MBIST and Automatic Test Pattern Generation (ATPG) to achieve test coverage goals.
• Working knowledge of JTAG 1149.1/6, IEEE1500, and IEEE1687.
• US citizenship preferred.

Culture & Benefits

• Fast-paced project environment with expectations for independent completion of DFT tasks.
• Collaborative work across cross-functional teams and stakeholders.
• Emphasis on discipline, thoroughness, and a methodical approach to problem-solving.