IC Design Engineer (DFT)

TL;DR

IC Design Engineer (DFT): Leading top-level DFT planning and integration for complex semiconductor designs with an accent on ATPG, ATE interface management, and test time optimization. Focus on implementing DFT across multi-power domains, performing STA and formal verification, and driving continuous flow improvements.

Location: Must be based in San Jose, CA, USA

Salary: $143,800 – $230,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Manage top-level DFT planning and integration for complex chip designs.
• Oversee ATPG and ATE interface, including bring-up and failure analysis.
• Drive test time reduction strategies to improve manufacturing efficiency.
• Perform synthesis, formal verification, and STA specifically for DFT modes.
• Implement DFT strategies across multi-power domain architectures.
• Troubleshoot DFT-related issues and drive continuous methodology improvements.

Requirements

• 10-12+ years of relevant experience in IC design and DFT.
• Extensive expertise with the Siemens Tessent tool suite.
• Strong background in ATPG, ATE, and DFT architecture.
• Proficiency in synthesis, formal verification, and STA.
• Experience managing DFT in multi-power domain environments.
• Must be authorized to work in the USA.

Culture & Benefits

• Competitive base salary with discretionary annual bonus.
• Equity participation including new hire grants and annual awards.
• Comprehensive medical, dental, and vision insurance plans.
• 401(k) retirement plan with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid holidays, sick leave, and vacation time.