Senior ASIC Digital Design Engineer (RTL)

TL;DR

Senior ASIC Digital Design Engineer (RTL): Developing high-performance RTL designs for ASIC/FPGA systems with an accent on correctness, timing closure, and formal verification. Focus on bus fabric integrity, clock domain crossing analysis, and driving designs from simulation to silicon.

Location: U.S. citizenship is required and must be able to obtain a DoD Secret security clearance

Salary: $142,166 – $150,000 per year

Company

Global provider of high-technology solutions, products, and services that enable customers to execute missions across all domains of operation.

What you will do

• Own RTL design tasks focusing on bus fabric integrity, clock domain crossings, and design-for-verification.
• Contribute to timing closure through synthesis, place and route, and static timing analysis (STA).
• Collaborate with dedicated verification teams to execute simulation plans and drive closure on failures.
• Participate in RTL code reviews and JIRA triage to maintain an actionable backlog.
• Provide technical input for program planning, schedule risk, and basis of estimates (BOEs) for proposals.
• Assist in evaluating foundry technologies, device libraries, IP cores, and EDA tooling.

Requirements

• Bachelor's degree in EE/CE (5+ years exp) or Master's degree (3+ years exp).
• U.S. citizenship is required.
• Ability to obtain a Department of Defense Secret security clearance.
• Proven experience as an RTL designer within structured design environments.
• Strong understanding of ASIC/FPGA engineering concepts, coding practices, and synthesis flows.
• Experience with clock domain crossing (CDC) analysis and reset sequencing.

Nice to have

• Experience contributing to ASIC tape-out efforts.
• Familiarity with FinFET process nodes (e.g., 7nm, 5nm).
• Knowledge of commercial foundry flows such as TSMC, GlobalFoundries, or Samsung.

Culture & Benefits

• Flexible work environment.
• Highly competitive benefits package.
• Opportunity for high levels of ownership over design tasks.
• Collaborative atmosphere within high-performance Integrated Product Teams.