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Senior Digital Design (AI)

50 600 - 69 600€
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Italy
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Senior Digital Design (AI): Leading full digital IC design flows for complex SoCs in NXP’s intelligent AI-at-the-Edge MCU teams with an accent on RTL design, synthesis, verification, and power-efficient architectures. Focus on developing high-performance digital architectures, resolving CDC and post-silicon issues, and integrating designs across analog, mixed-signal, and software domains.

Location: Catania, Italy

Gross annual base salary: €50,600–€69,600.

Company

hirify.global develops industrial and IoT edge-processing solutions, including microcontrollers and high-performance processors for real-time automation and connected applications.

What you will do

  • Lead the full digital IC design flow for complex SoCs, from specifications and architecture through RTL coding, synthesis, timing analysis, verification, and power analysis.
  • Contribute to design-for-testability implementation and verification, including simulation, formal verification, and hardware emulation.
  • Develop digital architectures and methodologies that meet performance, power, and area targets.
  • Collaborate with analog, mixed-signal, and software engineers to define interfaces and integrate complete systems.
  • Participate in post-silicon validation and debugging to resolve product-quality issues.
  • Mentor junior engineers, lead technical discussions, and prepare specifications, test plans, and design reviews.

Requirements

  • Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
  • At least 5 years of experience in digital IC design.
  • Expertise in Verilog and SystemVerilog for RTL design and verification.
  • Experience with EDA tools for synthesis, static timing analysis, formal verification, and simulation, including tools such as Design Compiler, Genus, PrimeTime, Formality, VCS, or QuestaSim.
  • Strong knowledge of digital design principles, clock-domain crossing, power integrity, and low-power design techniques.
  • Experience with Python, Perl, or Tcl scripting, mixed-signal integration, debugging, and collaborative technical leadership.

Culture & Benefits

  • Work as part of a newly established Catania engineering team covering analog and digital design, architecture, verification, DfT, and physical design.
  • Contribute to MCU products for intelligent AI-at-the-Edge applications.
  • Compensation follows the applicable Metalmeccanica Industria National Collective Labour Agreement.
  • The package may include annual incentives, equity, and additional benefits.
  • NXP applies fair, consistent, and transparent remuneration practices.

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