High Speed Analog I/O Designer (Analog)

TL;DR

High Speed Analog I/O Designer (Analog/Hardware): Designing and optimizing interface buffer chips for DDR/LP5/5X/6 and chiplets using FinFET process nodes with an accent on receiver (RX) and transmitter circuit design. Focus on improving sensitivity, linearity, and power consumption while minimizing the effect of parasitics and process variation.

Location: Must be based in San Jose, California, USA

Salary: $143,800 – $230,000

Company

hirify.global is a global leader in semiconductor and infrastructure software solutions.

What you will do

• Design, simulate, and optimize high-speed DDR circuits and chiplet I/Os.
• Develop and enhance transmitter and receiver circuits including CTLE, VGA, DFE, and slicers.
• Investigate circuit architectures to resolve bottlenecks in power, area, and performance.
• Oversee physical layout to mitigate parasitics and process variations.
• Conduct performance validation through thorough simulations and troubleshoot design issues.
• Analyze customer silicon data to drive future design enhancements.

Requirements

• Master's or Ph.D. in Electrical Engineering or a related field.
• Minimum 10 years of experience in analog design, specializing in high-speed RX and Analog-Front-End.
• Proven experience with FinFET technologies.
• Expertise in high-speed DDR and chip-chip interface design.
• Proficiency with Cadence Virtuoso, Maestro, Spectre, and HSPICE.
• Strong knowledge of signal integrity, timing analysis, and power management.

Culture & Benefits

• Competitive annual base salary with discretionary annual bonuses.
• Comprehensive equity grants (new hire and annual awards).
• Medical, dental, and vision insurance plans.
• 401(K) with company matching and Employee Stock Purchase Program (ESPP).
• Paid sick leave, vacation time, and company-paid holidays.