High Speed Analog I/O Designer

Location: San Jose, California, USA — onsite

Annual base salary: USD 143,800–230,000

Company

hirify.global develops semiconductor and interface technologies.

What you will do

• Design, simulate, and optimize high-speed DDR circuits and chiplet I/Os in advanced FinFET process nodes.
• Develop transmitter and receiver circuits, including CTLE, VGA, DFE, slicers, FIR filters, and voltage- and current-mode drivers.
• Investigate circuit architectures that improve power, area, performance, sensitivity, and linearity.
• Oversee physical layout to reduce parasitic and process-variation effects.
• Validate design performance and reliability through simulation, troubleshoot issues, and implement corrective actions.
• Analyze customer silicon data, prepare design reports, and collaborate with cross-functional chip teams.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Electronics Engineering, or a related field.
• At least 10 years of analog design experience focused on high-speed receiver and analog front-end design.
• Expertise in high-speed DDR I/O, chip-to-chip interface design, and optimization, including FinFET technologies.
• Knowledge of analog receiver and transmitter circuits, signal integrity, timing analysis, power management, and design-for-reliability concepts.
• Experience with custom digital design, serializers, deserializers, and analog design tools such as Cadence Virtuoso, Maestro, Spectre, and HSPICE.
• Strong analytical, communication, teamwork, and problem-solving skills.

Culture & Benefits

• Full-time employment with medical, dental, and vision plans.
• 401(k) participation with company matching and an employee stock purchase program.
• Discretionary annual bonus, new-hire equity grant, and potential annual equity awards.
• Paid holidays, sick leave, vacation, and applicable family leave.
• Employee Assistance Program.