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1 день назад

Principal Analog/Mixed Signal CAD Engineer (Semiconductors)

150 680 - 225 700$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Principal Analog/Mixed Signal CAD Engineer (Semiconductors): Architecting and maintaining advanced design automation infrastructure for high-speed analog, RF, and silicon photonics IC development with an accent on FinFET process nodes and simulation accuracy. Focus on developing next-generation automated AMS design flows, benchmarking EDA tools, and driving company-wide CAD best practices to improve engineering productivity.

Location: Must be based in Santa Clara, CA (Onsite 5 days per week)

Salary: $150,680 - $225,700 per annum

Company

hirify.global is a global leader in semiconductor solutions, providing essential infrastructure for data, cloud, and AI architectures.

What you will do

  • Architect and maintain analog/mixed-signal simulation environments for advanced CMOS FinFET and BiCMOS technologies.
  • Develop and support next-generation automated AMS design flows across global design teams.
  • Partner with analog designers and EDA vendors to resolve complex simulation and design flow challenges.
  • Collaborate with foundry and TCAD teams on device modeling and simulation accuracy.
  • Evaluate and benchmark new EDA tools and methodologies to enhance design productivity.
  • Define and implement custom circuit verification checks and model QA flows.

Requirements

  • BSEE with 10–15 years or MS/PhD with 5–10 years of professional experience.
  • Proven experience building and maintaining analog/mixed-signal design flows for advanced FinFET process technologies.
  • Strong hands-on experience with industry-standard AMS simulation tools (Cadence ADE, Spectre, Synopsys PrimeSim, AFS).
  • Solid understanding of schematic capture, parasitic extraction, and post-layout verification.
  • Must be eligible to access export-controlled information under U.S. law.
  • Must be able to work onsite in Santa Clara, CA, five days per week.

Nice to have

  • Experience with Cadence Virtuoso Schematic Editor, PDK integration, and CDF customization.
  • Programming or scripting proficiency in Python, TCL, Perl, or SKILL.
  • Familiarity with silicon photonics design flows and advanced circuit modeling techniques.

Culture & Benefits

  • Comprehensive financial well-being programs including an employee stock purchase plan.
  • Robust family support and mental health resources.
  • Recognition and service awards for professional milestones.
  • Opportunity to work in Silicon Valley’s semiconductor innovation hub on cutting-edge AI and cloud infrastructure.

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