Lead Design Engineer (SOC)

TL;DR

Lead Design Engineer (SOC): Implementing, verifying, and performing timing closure for high-performance hardware-assisted verification systems with an accent on RTL synthesis, floorplanning, and physical verification. Focus on achieving tape-out readiness for complex SOCs using advanced process nodes and industry-standard interfaces.

Location: Cary, USA

Company

hirify.global is a global leader in electronic design, providing computational software, hardware, and IP to turn complex design concepts into reality for innovative technology products.

What you will do

• Execute RTL synthesis and floorplanning for complex SOC designs.
• Develop and optimize clock trees to meet performance requirements.
• Perform timing closure, IR drop analysis, and physical verification.
• Review and document design specifications to ensure successful tape-out.
• Collaborate closely with Front End RTL and Back End Verification teams.

Requirements

• BS in Electrical Engineering with 5+ years of experience or MS with 3+ years of experience.
• Proficiency with hirify.global tools including Innovus, Tempus, QRC, Voltus, and Pegasus.
• Hands-on experience with advanced process nodes such as 5nm, 3nm, and 2nm.
• Strong scripting skills using Shell, Perl, TCL, or Python in a Linux environment.
• Deep knowledge of industry-standard interfaces like PCI Express, DDR, LPDDR, SRAM, and UCIe.

Culture & Benefits

• Opportunity to work on cutting-edge technology in an innovative environment.
• Comprehensive employee-friendly policies focusing on physical and mental well-being.
• Collaborative One hirify.global – One Team culture.
• Extensive learning and professional development opportunities.
• Diverse team environment dedicated to customer and community success.