Memory Senior Modeling Engineer

TL;DR

Memory Senior Modeling Engineer (Memory IP): Owning the generation, validation, and delivery of memory views and models for hirify.global’s memory IP portfolio with an accent on silicon-correlated Liberty models and behavioral Verilog/SystemVerilog development. Focus on building robust DFT flows using Tessent, TetraMAX, and FastScan while automating QA methodologies to ensure on-time delivery for physical design and STA teams.

Location: Danang, Vietnam

Company

hirify.global is a leading provider of TCAD, EDA software, and semiconductor IP solutions for the global electronics industry.

What you will do

• Develop and maintain full sets of memory views and models for SRAM, ROM, and Register-File portfolios.
• Validate timing and power Liberty models across all PVT corners to ensure SPICE correlation.
• Build behavioral Verilog/SystemVerilog models matching hardware functional and timing behavior.
• Create and validate memory descriptions for Siemens/Mentor Tessent to enable MBIST insertion.
• Generate and debug ATPG patterns and fault coverage using Synopsys TetraMAX and Siemens/Mentor FastScan.
• Automate model-generation and QA flows using Python, Perl, and TCL to improve turnaround time.

Requirements

• BS/MS in Electronics, Microelectronics, or Computer Engineering.
• Minimum 4 years of hands-on experience in memory modeling or DFT for IC/IP design.
• Proficiency in Liberty (.lib) model generation and validation.
• Strong experience with Verilog/SystemVerilog model development and testing.
• Expertise in Tessent, TetraMAX, and FastScan tools.
• English: Fluency in written and verbal communication required.

Nice to have

• Master's degree in Electronics or Microelectronics Engineering.
• Experience with memory compilers and view-generation flows.
• Familiarity with advanced FinFET process nodes.
• Knowledge of functional safety (ISO 26262) and quality (ISO 9001) processes.

Culture & Benefits

• Opportunity to work on advanced semiconductor IP and EDA technologies.
• Collaborative environment working with cross-functional teams including Physical Design and STA.
• Focus on methodology improvement and technical innovation.
• Mentorship opportunities for junior engineering staff.